Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis
Reexamination Certificate
2008-01-15
2008-01-15
Cheung, Mary D. (Department: 3694)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Reexamination Certificate
active
07320082
ABSTRACT:
A memory device with multiple clock domains. Separate clocks to different portions of the control circuitry create different clock domains. The different domains are sequentially turned on as needed to limit the power consumed. The turn on time of the domains is overlapped with the latency for the memory access to make the power control transparent to the user accessing the memory core. The memory device can dynamically switch between a fast and a slow clock depending upon the needed data bandwidth. The data bandwidth across the memory interface can be monitored by the memory controller, and when it drops below a certain threshold, a slower clock can be used. The clock speed can be dynamically increased as the bandwidth demand increases.
REFERENCES:
patent: 4528661 (1985-07-01), Bahr et al.
patent: 4744062 (1988-05-01), Nakamura et al.
patent: 4792926 (1988-12-01), Roberts
patent: 5251178 (1993-10-01), Childers
patent: 5268639 (1993-12-01), Gasbarro
patent: 5335206 (1994-08-01), Kawamoto
patent: 5337285 (1994-08-01), Ware et al.
patent: 5359722 (1994-10-01), Chan
patent: 5384737 (1995-01-01), Childs et al.
patent: 5432468 (1995-07-01), Moriyama et al.
patent: 5452401 (1995-09-01), Lin
patent: 5455923 (1995-10-01), Kaplinsky
patent: 5457790 (1995-10-01), Iwamura
patent: 5471607 (1995-11-01), Garde
patent: 5481731 (1996-01-01), Conary
patent: 5498990 (1996-03-01), Leung
patent: 5524249 (1996-06-01), Suboh
patent: 5585745 (1996-12-01), Simmons et al.
patent: 5586332 (1996-12-01), Jain
patent: 5598376 (1997-01-01), Merritt et al.
patent: 5615169 (1997-03-01), Leung
patent: 5623677 (1997-04-01), Townsley et al.
patent: 5629897 (1997-05-01), Iwamoto et al.
patent: 5655113 (1997-08-01), Leung et al.
patent: 5666322 (1997-09-01), Conkle
patent: 5666324 (1997-09-01), Kosugi
patent: 5673398 (1997-09-01), Takeda
patent: 5677849 (1997-10-01), Smith
patent: 5687183 (1997-11-01), Chestley
patent: 5696729 (1997-12-01), Kitamura
patent: 5726650 (1998-03-01), Yeoh et al.
patent: 5742194 (1998-04-01), Saeki
patent: 5754838 (1998-05-01), Shibata et al.
patent: 5758132 (1998-05-01), Strahlin
patent: 5768213 (1998-06-01), Jung et al.
patent: 5790839 (1998-08-01), Luk
patent: 5793227 (1998-08-01), Goldrian
patent: 5796673 (1998-08-01), Foss et al.
patent: 5796995 (1998-08-01), Nasserbakht et al.
patent: 5802356 (1998-09-01), Gaskins et al.
patent: 5815462 (1998-09-01), Konishi
patent: 5815693 (1998-09-01), McDermott et al.
patent: 5822255 (1998-10-01), Uchida
patent: 5845108 (1998-12-01), Yoo et al.
patent: 5860125 (1999-01-01), Reents
patent: 5880998 (1999-03-01), Tanimura
patent: 5884100 (1999-03-01), Normoyle et al.
patent: 5886946 (1999-03-01), Ooishi
patent: 5890195 (1999-03-01), Rao
patent: 5910930 (1999-06-01), Dieffenderfer et al.
patent: 5917760 (1999-06-01), Millar
patent: 5918058 (1999-06-01), Budd
patent: 5930197 (1999-07-01), Ishibashi
patent: 5955904 (1999-09-01), Kawasaki
patent: 5987620 (1999-11-01), Tran
patent: 6014339 (2000-01-01), Kobayashi
patent: 6037813 (2000-03-01), Eto et al.
patent: 6088774 (2000-07-01), Gillingham
patent: 6128700 (2000-10-01), Hsu
patent: 6134638 (2000-10-01), Olarig et al.
patent: 6209071 (2001-03-01), Barth et al.
patent: 6226723 (2001-05-01), Gustavson
patent: 6259288 (2001-07-01), Nishimura
patent: 6263448 (2001-07-01), Tsern et al.
patent: 6442644 (2002-08-01), Gustavson et al.
patent: 552975 (1993-07-01), None
patent: 94112140.2 (1994-03-01), None
patent: 0638858 (1995-02-01), None
patent: 96308132.8 (1996-11-01), None
patent: 0778575 (1997-06-01), None
patent: 61-160129 (1986-07-01), None
patent: 61-160130 (1986-07-01), None
patent: 61-245255 (1986-10-01), None
patent: 62-135949 (1987-06-01), None
patent: 1-163849 (1989-06-01), None
patent: 6-103153 (1994-04-01), None
patent: 09 034580 (1997-02-01), None
“Chips & Technologies: Chips Introduces First IBM”, Jul. 20, 1987, del 30-compatible Vlsi Chipset.
JC-42.3 Executive Committee Meeting No. 75, May 24, 1995, New Orleans.
Minutes of meeting and presentations made at JC-42.3 Committee on RAM Memories, Meeting No. 75, May 24, 1995, New Orleans.
Minutes of meeting and presentations made at JC-42.3 Committee on RAM Memories, Meeting No. 76, Sep. 11, 1995, Crystal City, VA.
Bursky, “Memory-CPU Interface Speeds Up Data Transfers”.
Choi, “16Mbit Synchronous DRAM with 125Mbyte/sec Data Rate”.
Gary et al., “The PowerPC™ 603 Microprocessor: A Low-Power Design for Portable Applications”.
Gillingham, “SLDRAM Architectural and Functional Overview,” SLDRAM Consortium, Aug. 29, 1997.
Han, “Skew Minimization Techniques for 256M-bit Synchronous DRAM and beyond,” 1996 Symposium on VLSI Circuits Digest of Technical Papers.
Horowitz, “PLL Design for a 500 MB/s Interface,” 1993 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, Feb. 25, 1993.
Kodama, “A 150-MHz 4-Bank 64M-bit SDRAM with Address Incrementing Pipeline Scheme,” 1994 Symposium on VLSI Circuits Digest of Technical Papers, 1994.
Kushiyama, “A 500-Megabyte/s Data-Rate 4.5M DRAM,” IEEE Journal of Solid-State Circuits, vol. 28 No. 4, Apr. 1993.
Kushiyama, “500Mbyte/sec Data-Rate 512 Kbits x 9 DRAM Using a Novel I/O Interface,” 1992 Symposium on VLSI Circuits Digest of Technical Papers, 1992.
Lee et al., “A 2.5 V CMOS Delay-Locked Loop for an 18 Mbit, 500 Megabyte/s DRAM”.
Nicol, “A Scalable Pipelined Architecture for Fast Buffer SRAM's,” IEEE Journal of Solid-State Circuits, vol. 31, No. 3, Mar. 1996.
Saeki et al., “A2.5ns Clock Access, 250MHz 256Mb SDRAM with Synchronous Mirror Delay,”.
Sakai, “A Synchronous DRAM with New High-Speed I/O Lines Method for the Multimedia Age,” IEICI Trans. Electron., vol. E78-C, No. 7, Jul. 1995.
Takai, “250 Mbyte/s Synchronous DRAM Using a 3-Stage-Pipelined Architecture,” IEEE Journal of Solid-State Circuits, vol. 29, No. 4, Apr. 1994.
Yoo, “A 150HMz 8-Banks 256M Synchronous DRAM with Wave Pipelining Methods,” 1995 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, Feb. 17, 1995.
IEEE, “Draft Standard for A High-Speed Memory Interface (SyncLink)”, 1996.
“IEEE Standard for High-Bandwidth Memory Interface Based on Scalable Coherent Interface SCI Signaling Technology (RamLink)” 1996.
MoSys, Inc., “MD904 to MD920, ½ to 2½ MByte Multibank® DRAM (DRAM9®)” MoSys Data Sheet, Feb. 21, 1997.
Rambus, Inc., “NEC 18Mb Rambus DRAM Core Interface,” Aug. 9, 1992.
Rambus Inc., “p5 18Mb RDRAM Test Modes,” Aug. 3, 1992.
Rambus, Inc., “Rambus Interface Technical Description” Jan. 20, 1992.
Rambus, Inc., “Rambus Interface Technical Description,” Aug. 18, 1992.
Rambus, Inc., “RDRAM Design Guide,” Apr. 20, 1995.
Rambus Inc, 8/9-Mbit (1M x 8/9) and 16/18 (2M x 8/9) RDRAM Data Sheet, Mar. 1996.
Rambus Inc, 16/18Mbit (2Mx8/9) & 64/72Mbit (8Mx8/9) Concurrent RDRAM Data Sheet, Jul. 1996.
SLDRAM Consortium Data Sheet, “400 Mb/s/pin SLDRAM Advance Data Sheet,” Aug. 27, 1997.
SyncLink Consortium, “SyncLink Feasibility v1.1,” Apr. 30, 1996.
Bursky, “Memory-CPU Interface Sppeds Up Data Transfers,” Electronic Design, pp. 137-142, Mar. 19, 1992.
Choi, “16Mbit Synchronous DRAM with 125Mbyte/sec Data Rate,” Symposium on VLSI Circuits, Digest of Technical Papers, pp. 65-66, 1993.
Gary et al., “The PowerPC™ 603 Microprocessor: A Low-Power Design for Portable Applications,” IEEE Design & Test of Computers, Winter, 1994.
Lee et al., “A 2.5 V CMOS Delay-Locked Loop for an 18 Mbit, 500 Megabyte/s DRAM,” J. of Solid State Circuits, vol. 29, No. 12, pp. 1491-1496, Dec. 1994.
Lines et al., “High Speed Circuit Techniques in a 150Hz 64M SDRAM,” Proceedings of memory Technology, Design & Testing Int'l Workshop, San Jose, California, Aug. 11,
Barth Richard M.
Hampel Craig E.
Stark Donald C.
Tsern Ely K.
Cheung Mary D.
Morgan & Lewis & Bockius, LLP
Rambus Inc.
LandOfFree
Power control system for synchronous memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Power control system for synchronous memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Power control system for synchronous memory device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2802749