Post write buffer for a dual clock system

Details Post write buffer for a dual clock system Post write buffer for a dual clock system

2000-01-07

2002-12-24

Wong, Peter (Department: 2781)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S306000, C710S033000, C713S400000, C713S500000, C713S600000

Reexamination Certificate

active

06499080

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
This invention relates in general to the field of computer data bus systems, and more particularly to a post write buffer for a dual clock system.
BACKGROUND OF THE INVENTION
A computer is made up of several components which must communicate in order for the computer to perform its functions. This communication takes place across an internal bus. The internal bus is a collection of wires through which data, a destination address, and other information is transmitted from one part of a computer to another. This bus is sometimes referred to as a host data bus. The host data bus is connected to a configuration block which contains several configuration and control registers for the computer. These are referred to collectively as destination registers. One of the functions of the host data bus is to transfer data and other information into the different registers of the configuration block. Although registers in the configuration block can be up to 32 bits wide, the host data bus is often 8 or 16 bits wide. Thus, multiple transfers are necessary in order to write the necessary information to the configuration block registers.
Although it is preferable to have the host data bus and configuration block registers operate on the same clock source, thereby eliminating any clock synchronization issues, these two key components of a computer system often are attached to separate clock sources operating at different frequencies. Thus, before data and information from the host data bus can be transferred to the configuration block registers, the two clock sources must be synchronized. This requires the host data bus to wait which prevents it from performing other functions. The clock synchronization process often results in a bottleneck of data and information waiting to be transferred to different parts of the computer.
Current computer systems have a clock synchronization circuit which is invoked any time that the host data bus, clocked by a first clock source, needs to write to a configuration block register which is clocked by a second clock source. The clock synchronization circuit requires four clock cycles of the clock which controls the host data bus and three clock cycles of the clock which controls the destination register. Some of the disadvantages associated with the current solutions to the aforementioned dual clock problem are that the host data bus is unavailable to transfer data and information to other parts of the computer, and the bandwidth of the bus is wasted.
Due to the aforementioned problems, current methods of connecting a host data bus and destination registers clocked by separate clock sources are inefficient and often result in bottlenecks within the host data bus.
SUMMARY OF THE INVENTION
From the foregoing, a need has arisen for an improved system and method for transferring data from a host data bus controlled by a first clock source to a destination register controlled by a second clock source which frees the host data bus to perform other functions while a clock synchronization process occurs to allow the data to be written to the destination register. In accordance with the present invention, a post write buffer for a dual clock system is provided which substantially eliminates or reduces- disadvantages or problems associated with conventional interconnections between a host data bus and destination registers.
According to one embodiment of the present invention, there is provided a post write buffer which is coupled to both the host data bus and the configuration block and functions to buffer the data in the host data bus until registers in the configuration block are available to receive it. The post write buffer consists of an address decoder and an address buffer, a data buffer, and a write enable circuit for each of four bytes corresponding to the four bytes of the destination register in the configuration block. The post write buffer is installed in systems in which the host data bus is controlled by a first clock source and all or part of the destination registers which may reside in the configuration block are controlled by a second clock source.
The present invention provides various technical advantages over current computer system data buses. It eliminates the need for the host data bus to remain idle while waiting for the clocks to be synchronized so that data can be transferred from the host data bus to the destination register. Also, the bandwidth of the host data bus is more fully utilized since the data bus does not need to remain idle. This substantially reduces the bottleneck which often occurs in the host data bus thereby increasing the performance of the computer as a whole. Other examples may be readily ascertainable by those skilled in the art from the following figures, description, and claims.


REFERENCES:
patent: 5381529 (1995-01-01), Matsushima
patent: 5991861 (1999-11-01), Young
patent: 6377650 (2002-04-01), Deng et al.

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