Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-06-05
2001-05-15
Quach, T. N. (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S786000, C438S798000
Reexamination Certificate
active
06232217
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to methods of forming metal interconnects in semiconductor devices and specifically to forming such metal interconnects within FSG ILD and IMD layers.
BACKGROUND OF THE INVENTION
Metal interconnects are attacked by fluorine (F) species from fluorinated silica glass (FSG) interlevel dielectric (ILD) or intermetal dielectric (IMD) layers. The F species attacks on the metal interconnects forms metal fluorides, which are non-conducting and causing electrical resistance or loose contacts.
For example, U.S. Pat. No. 5,244,535 to Ohtsuka et al. describes a method of manufacturing a semiconductor device including a nitrogen-containing plasma treatment of contact holes. The contact holes are etched through an insulation layer (for example SiO
2
) with a fluorine-based gaseous plasma, and the contact holes are then immediately flooded with the nitrogen-containing plasma that inhibits formation of reaction products on the exposed portion of the contact holes.
U.S. Pat. No. 5,643,407 to Chang describes a method of forming via openings through an intermetal dielectric (IMD) layer (comprised of spin-on-glass (SOG) sandwiched between two layers of silicon oxide (SiO
2
)) to an underlying patterned first metal layer. A vacuum bake is used to remove moisture from the exposed SOG layer within the via opening and then a nitrogen plasma treatment converts the SOG layer from an organic to an inorganic material. The inorganic SOG layer material has less moisture absorption, and suppresses outgassing from the rest of the organic SOG layer to prevent poisoned via metallurgy.
U.S. Pat. No. 5,970,376 to Chen describes a method for forming a via through a dielectric layer within a microelectronics fabrication. A via is formed through a low dielectric constant dielectric layer (formed from a silsequioxane SOG dielectric material) by a fluorine-containing plasma etch method. The fluorine-containing plasma etch method also simultaneously forms a fluorocarbon polymer residue layer on a sidewall of the etched via. A plasma treatment is then applied to the via to form a plasma treated fluorocarbon polymer residue layer. The plasma treated fluorocarbon polymer residue layer on the sidewall of the via may then be stripped, and is stripped, with an oxygen containing plasma.
U.S. Pat. No. 5,976,626 to Matsubara et al. describes a method of manufacturing a semiconductor without corrosion in wiring, for example. A silicon oxide film is formed on a substrate, covering a first wiring formed with a silicon oxide film therebetween. A thick-film inorganic SOC film is then coated on the silicon oxide film and a thermal treatment is then applied. A silicon oxide film is then formed and a via hole is then formed through to the first wiring. A thermal treatment at 150-550° C. and not more than 10
−3
Torr pressure is then carried out with a portion of the thick-film inorganic SOC film exposed at a side surface of the via hole. Residual gas, such as CO
2
and H
2
O adsorbed to the side surface of the via hole is released so that subsequently formed wiring within the via hole will not be corroded.
U.S. Pat. No. 5,763,010 to Guo et al. describes a method of stabilizing halogen-doped silicon oxide film to reduce halogen atoms migrating from the film during subsequent processing steps. A halogen-doped film is deposited over a substrate and is then subjected to a degassing step by briefly heating the film to between about 300 and 550° C. before deposition of a diffusion barrier layer. The heat treatment is thought to remove loosely bonded halogen atoms from the halogen-doped film. In a preferred embodiment, the halogen-doped silicon oxide film is FSG film that is subjected to a degassing treatment for between about 35 and 50 seconds.
U.S. Pat. No. 5,827,785 to Bhan et al. describes a method and apparatus for improving film stability of a halogen-doped silicon oxide layer. A process gas is introduced including a first and second halogen source into a deposition chamber along with silicon and oxygen sources. A plasma is then formed from the process gas to deposit a halogen-doped layer over a substrate within the chamber. The additional halogen source, i.e. the second halogen source, is believed to enhance the etching effect of the film and this enhanced etching component of the film deposition improves the film's gap-fill capabilities and helps stabilize the film. In the preferred embodiment, the halogen-doped film is a fluorosilicate glass (FSG) film; SiF
4
is the first halogen source; TEOS is the source of the silicon; and the second halogen source is either F
2
or NF
3
.
U.S. Pat. No. 5,904,566 to Tao et al. describes a method for forming a via through a nitrogenated silicon oxide layer. A reactive ion etch (RIE) plasma etch is used to create a via opening is formed through a nitrogenated silicon oxide layer to an underlying substrate. The RIE method uses an etchant gas composition comprising: a perfluorocarbon having a carbon: fluorine atomic ratio of at least about 1:3; oxygen; and argon.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a method of forming a metal interconnect within a fluorinated silica glass dielectric layer while preventing outgassing from the fluorinated silica glass dielectric layer.
Another object of the present invention is to provide a method of forming a metal interconnect in a via opening within a fluorinated silica glass dielectric layer while eliminating fluorine species on the exposed surface of the fluorinated silica glass dielectric layer within the via opening to reduce the possibility of forming metal fluorides.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a semiconductor structure having a semiconductor device structure formed therein is provided. A metal line is formed over the semiconductor structure. The metal line being electrically connected with the semiconductor device structure. An insulating layer is formed over the semiconductor structure, covering the metal line. A fluorinated silica glass dielectric layer is formed over the insulating layer. The fluorinated silica glass dielectric layer is planarized to form a planarized fluorinated silica glass dielectric layer. The planarized fluorinated silica glass dielectric layer and the insulating layer are patterned to form a via opening to the metal line, and exposing portions of the patterned fluorinated silica glass dielectric layer within the via opening. The via opening is treated with a plasma selected from the group comprising an N-containing plasma, an H-containing plasma, and a combination thereof. A metal interconnect is then formed within the via opening.
REFERENCES:
patent: 5244535 (1993-09-01), Ohtsuka et al.
patent: 5643407 (1997-07-01), Chang
patent: 5763010 (1998-06-01), Guo et al.
patent: 5827785 (1998-10-01), Bhan et al.
patent: 5904566 (1999-05-01), Tao et al.
patent: 5970376 (1999-10-01), Chen
patent: 5976626 (1999-11-01), Matsubara et al.
patent: 6008118 (1999-12-01), Yeh et al.
patent: 6008120 (1999-12-01), Lee
patent: 6074941 (2000-06-01), Hsieh et al.
patent: 6077784 (2000-06-01), Wu et al.
Ang Arthur
Yi Xu
Chartered Semiconductor Manufacturing Ltd.
Pike Rosemary L. S.
Quach T. N.
Saile George O.
Stanton Stephen G.
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