Post-spacer LDD implant for shallow LDD transistor

Details Post-spacer LDD implant for shallow LDD transistor Post-spacer LDD implant for shallow LDD transistor

1997-03-17

1999-11-23

Fahmy, Wael M.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438301, 438305, 438306, 438307, G01L 21336

Patent

active

059899646

ABSTRACT:
Broadly speaking, the present invention contemplates a semiconductor manufacturing process in which LDD regions of a semiconductor transistor are implanted after the heavily doped regions without requiring the removal of spacer structures from the sidewalls of the transistor gate. A semiconductor substrate is provided. The semiconductor substrate includes a channel region laterally displaced between first and second lightly doped regions. The first and second lightly doped regions are laterally displaced between first and second heavily doped regions of the semiconductor substrate. A gate dielectric is formed on an upper surface of the semiconductor substrate. A conductive gate structure is then formed on the gate dielectric. The conductive gate structure is aligned over the channel region of the semiconductor substrate. First and second spacer structures are then formed on first and second sidewalls of the conductive gate. The first and second spacer structures extend laterally from the first and second sidewalls of the conductive gate such that the first and second spacer structures cover the first and second lightly doped regions of the semiconductor substrate. A projected range characteristic of the first and second spacer structures is greater than a projected range characteristic of the conductive gate structures. A first impurity distribution is then introduced into the semiconductor substrate. An interlevel dielectric layer is then deposited on the underlying topography and planarized. A projected range characteristic of the interlevel dielectric layer is approximately equal to a projected range characteristic of the first and second spacer structures. A second impurity distribution is then implanted into the semiconductor substrate through the interlevel dielectric layer.

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