Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2007-10-04
2008-11-11
Pert, Evan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S360000, C257S499000, C257S203000, C257SE23001
Reexamination Certificate
active
07449752
ABSTRACT:
A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.
REFERENCES:
patent: 6040604 (2000-03-01), Lauvray et al.
patent: 6187680 (2001-02-01), Costrini et al.
patent: 6200888 (2001-03-01), Ito et al.
patent: 6229221 (2001-05-01), Kloen et al.
patent: 6232147 (2001-05-01), Matsuki et al.
patent: 6383916 (2002-05-01), Lin
patent: 6459135 (2002-10-01), Basteres et al.
patent: 6472745 (2002-10-01), Iizuka
patent: 2002/0158334 (2002-10-01), Vu et al.
patent: 1 039 544 (2000-09-01), None
patent: 2000 216264 (2000-08-01), None
“Processing Thick, Multilevel Polyimide Films for 3-D Stacked Memory”, by Michael D. Caterer et al., IEEE Trans. on Advanced Packaging, vol. 22, No. 2, May 1999, pp. 189-199.
“Power Distribution Techniques for VLSI Circuits”, by William S. Sang et al., IEEE Jrnl. of Solid State Circuits, vol. SG-21, No. 1, Feb. 1986, XP-002317942, pp. 150-156.
“Influence of the Series Resistance of On-Chip Power Supply Buses on Internal Device Failure After ESD Stress”, by H. Terletzki et al., XP 000413126, 1993 IEEE, vol. 40, No. 11, Nov. 1993, pp. 2081-2083.
Lee Jin-Yuan
Lin Mou-Shiung
Ackerman Stephen B.
Megica Corporation
Pert Evan
Rosemary L. S. Pike
Saile Ackerman LLC
LandOfFree
Post passivation interconnection schemes on top of the IC chips does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Post passivation interconnection schemes on top of the IC chips, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Post passivation interconnection schemes on top of the IC chips will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4028573