Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1995-01-09
2001-06-05
Tu, Christine T. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S735000
Reexamination Certificate
active
06243843
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to boundary scan testing. More particularly, this invention relates to a post-mission test method for assuring the integrity of the boundary scan test.
2. Background Art
Boundary scan is a testing standard formally known as IEEE/ANSI Standard 1149.1-1990. Boundary scan is applied principally at the Integrated Circuit (IC) level. Boundary scan ICs are designed with shift registers or cells place between each device pin and the internal logic of the IC. These cells allow an operator to control and observe what happens at each input and output pin. When these cells are connected together they form a data register chain, called the Boundary Register, defining a scan path. Additional registers within a boundary scan IC include and Instruction Register, which decodes instruction bits that allow the IC to perform various functions; a Bypass Register, which provides a one-bit scan path that minimizes the distance between the scan input and the scan output; an Identification Register, called the IDCODE Register, which identifies the device and manufacturer; and other designer-specified data registers, which typically perform internal test functions.
Boundary scan ICs are designed to be linked together into chains. A simple chain includes boundary scan ICs with common test clock terminals (TCK) and test mode select terminals (TMS); and with the scan paths of the ICs linked together by connecting a test data out (TDO) terminal of one IC to the test data in (TDI) terminal of the following IC.
For purposes of the following discussion, testing with boundary scan principles and techniques, and boundary scan IC chips and scan paths is referred to as boundary scan testing. A mission test includes a complete single test, such as an interconnect test, a connection test or an interaction test, as well, IC internal logic tests. A test frame refers to a portion of a mission test involving shifting in a test vector, writing the test vector to the test logic, which is part of the testing infrastructure, capturing a test result and shifting out the test results.
A more detailed discussion of boundary scan testing is provided in IEEE Standard 1149.1-1990, “IEEE Standard Test Access Port and Boundary Scan Architecture,” IEEE Standards Board; “HP Boundary Scan Tutorial and BSDL Reference Guide,” Hewlett-Packard Company, HP Part Number E1017-90001, 1990; and Kenneth P. Parker,
The Boundary
-
Scan Handbook
, (Kluwer Academic Publishers, 1992); each of which is incorporated herein by reference.
Prior to executing useful mission testing, an operator has to be able to depend upon the chain of register cells being in operational order. Therefore, the basic function of the chain needs to be assured before the results of the mission test can be relied upon. Testing the integrity of the chain prior to executing boundary scan testing is discussed in detail in
The Boundary
-
Scan Handbook
at pp. 114-117.
However, it has been identified by the inventors that it is possible that during execution of a mission test, an operational flaw in the scan path may occur, causing the integrity of the scan path to be compromised. For example, a test induced ground bounce or a timing condition may cause the integrity of the mission test to be compromised after the pre-mission test integrity test has been performed and, more particularly, during mission test execution.
If this occurs, the mission test results will be inaccurate. Diagnosing the inaccurate test results will result in invalid or erroneous diagnostic information. If this diagnostic information is relied upon, a significant amount of a technician's time may be wasted in attempting to repair faults that, in reality, do not exist. What it is needed is a method to detect when such an operational flaw occurs so that invalid test results can be discarded.
SUMMARY OF THE INVENTION
The invention is a method for performing and assuring the integrity of a mission test. The method includes the steps of checking the integrity of the mission test after mission test execution and prior to mission test diagnosis. In particular, after the mission test has been executed, the integrity of the mission test is confirmed based on a scan path bit length comparison.
The method in accordance with the invention comprises the steps of performing a mission test on a circuit, determining (after performance of the mission test) an actual bit length of a scan path through the circuit, comparing the actual bit length to an expected bit length and indicating the invalidity of the mission test if the actual bit length is not equal to the expected bit length.
The actual bit length of the scan path is determined at the end of mission test execution by shifting a signature pattern through the scan path. Specifically, the signature pattern shifted into the scan path is compared to the signature pattern shifted out. Based on this comparison, the actual bit length of the scan path can be determined.
Preferably, the signature pattern is shifted in concurrently with the shifting out of the last test result of the mission test. The length of the scan path can be determined based on the number of clock cycles required to shift the signature pattern through the scan path. This is most readily accomplished by shifting the scan path a number of clock cycles equal to twice the expected length of the scan path. If the signature pattern is equal in length to the scan path, then this will result in the test pattern traveling through the scan path with the last bit exiting the scan path on the last clock cycle. The last n bits out the scan path should then match the n bits of the signature pattern (for an n bit long scan chain). If the bits of the pattern out do not match the bits of the pattern in, then the actual length of the scan path does not match the expected length.
The method for testing a circuit board includes the steps of generating a group of mission test vectors, serially shifting each test vector into the scan path, writing each test vector to the test logic, capturing each response pattern, serially shifting each response pattern out of the scan path, shifting a signature pattern into the scan path, shifting the signature pattern out of the scan path, determining an actual bit length of the scan path, comparing the actual bit length with an expected bit length and indicating an invalid mission test if the actual bit length does not equal the expected bit length.
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Jarwala et al., “A New Framework for Analyzing Test Generation and Diagnosis Algothrithms for Wiring Interconnects,” 1989 Int'l Test Conf, 1989 IEEE, Paper 3.3, pp. 63-70.
de Jong, “Boundary Scan Test Used at Board Level-Moving Towards Reality,” 1990 Int'l Test Conf, 1990 IEEE, Paper 9.2, pp. 235-242.
Hansen, “Testing Conventional Logic and Memory Clusters Using Boundary Scan Devices as Virtual ATE Channels,” 1989 Int'l Test Conf, 1989 IEEE, Paper 7.1, pp. 166-173.
Kashiwabara et al., “Permutation Layout With Arbitrary Between-pins Capacities,” 1990 IEEE, pp. 340-343.
McBean et al., “Bridging Fault Algorithms for a Boundary Scan Board,” pp. 6/1-6/8.
Cheng et al., “Optimal Diagnostic Methods for Wiring Interconnects,” 1992 IEEE Transactions on a Computer-Aided Design, vol. II, No. 9, Sep. 1992, pp. 1161-1166.
McBean et al., “Testing Interconnect: A Pin Adjacency Approach,” 1993 IEEE, pp. 484-490.
Yau et al., “A Unified Theory for Designing Optimal Test Generation and Diagnosis Algorithms for Board Interconnects,” 1989 Int'l Test Conf, 1989 IEEE, Paper 3.4, pp. 71-77.
Cheng et al., “Diagnosis for Wiring Interconnects,” 1990 Int'l Test Conf., 199
Oresjo Stig
Parker Kenneth P.
Agilent Technologie,s Inc.
Tu Christine T.
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