Post gate etch cleaning process for self-aligned gate mosfets

Details Post gate etch cleaning process for self-aligned gate mosfets Post gate etch cleaning process for self-aligned gate mosfets

1999-03-18

2001-06-05

Powell, William (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

C134S001200, C216S067000, C216S079000, C438S714000, C438S715000, C438S734000, C438S725000

Reexamination Certificate

active

06242350

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to processes for the manufacture of semiconductor devices and more particularly to processes for forming self-aligned polysilicon gate field effect transistors.
(2) Description of prior art and background to the invention
Complimentary metal oxide semiconductor(CMOS) field effect transistor(FET) technology involves the formation n-channel FETs(NMOS) and p-channel FETs(PMOS) in combination to form low current, high performance integrated circuits. The complimentary use of NMOS and PMOS devices, typically in the form of a basic inverter device, allows a considerable increase of circuit density of circuit elements by reduction of heat generation. The increase in device density accompanied by the shrinkage of device size has resulted in improved circuit performance and reliability as well as reduced cost. For these reasons CMOS integrated circuits have found widespread use, particularly in digital applications.
A MOSFET is formed by a self-aligned gate process. Referring to
FIG. 1
, there is shown a cross section of a wafer
10
illustrating the formation of a polycide gate MOSFET. A gate oxide
12
is grown on an exposed surface of the silicon wafer
10
and a conductive layer
14
is deposited over it. The conductive layer
14
is typically a polycide layer which is a composite layer comprising a bottom portion formed of polysilicon and a top portion formed of a transition metal silicide, for example WSi
x
.The term polycide is commonly used to refer to a silicide-over-polysilicon composite layer. To pattern a polycide gate electrode, a photoresist layer
16
is deposited over the polycide layer
14
and patterned by photolithography. In order to reduce surface reflections from the polycide during the photolithography, an organic BARC(bottom anti reflective coating)
18
is often included under the photoresist layer
16
.
Referring to
FIG. 2
, the polycide layer
14
is etched to the gate oxide
12
by an anisotropic plasma etching technique, for example reactive ion etching (RIE), to forming the gate electrode
20
. The etchants used generally contain Cl
2
and HBr and are selected to provide a high polysilicon-to-silicon oxide selectivity so that the gate oxide layer functions as an etch stop and further permits an over etch period whereby residual pockets of polysilicon are removed.
After the gate electrode
20
has been patterned, residues of various types remain behind on the wafer which must be removed by a cleaning process.
FIG. 2
shows a cross section of a polycide gate electrode after the gate electrode
14
has been defined by a plasma etch. A polymer veil
22
is formed over the residual photoresist layer. The veil
22
formation results from the use of HBr in the final polysilicon etch step. HBr is used in this process to achieve a high etch rate selectivity of polysilicon to silicon oxide during the last stages of etching and in required over etch period. A second polymer
24
forms on the sidewalls of the gate electrode
20
. Additional patches
26
of this polymer are also found on the surface of the gate oxide
12
. These polymer deposits result from chemical reactions which occur during the plasma etching process and are silicaceous as well as carbonaceous. During plasma etching, the sidewall polymer
24
plays the important role of protecting the walls of the gate electrode from etchant undercutting, thereby enabling a vertical sidewall profile.
In conventional practice the residual photoresist layer
16
and the organic BARC
18
are removed by ashing in a plasma containing oxygen. The polymer layers cannot be removed by the conventional oxygen ashing process and are removed by a dip in dilute aqueous HF or in NH
4
OH.
After polymer is removal, the wafer is subjected to RCA cleaning. The RCA cleaning method which uses NH
4
OH/H
2
O
2
and HCI/H
2
O
2
solutions is well known and has been used for many years to clean particulates and other chemical residues from silicon wafers. A discussion of the RCA technique may be found in Wolf, S. and Tauber, R. N., “Silicon Processing for the VLSI Era”, Vol.1, Lattice Press, Sunset Beach, Calif., (1986),p516ff. The ammoniacal solution is effective for removing organic residues and particulates while the acidic solution removes metallic contaminants.
The RCA cleaning process, by itself, is effective at removing the sidewall polymer but cannot remove the polymer veil, necessitating the inclusion of the HF or NH
4
OH dip prior to the RCA process. Unfortunately, both HF and NH
4
OH attack the gate oxide which lies exposed after the gate etch. Etching with dilute HF to properly remove all the polymer also removes some 20 to 40 Å of the gate oxide. The oxide loss when NH
4
OH is used is only slightly less. This problem is of particular concern for gate oxides less than 50 Angstroms thick when all or nearly all of the remaining gate oxide may be lost. Nguyen, et. al., U.S. Pat. No. 5,597,983 cite the use of tetramethyl ammonium hydroxide(TMAH) to remove polymer from plasma etched via openings in over aluminum. However, TMAH not only etches silicon oxide at a measurable rate it also attacks silicon at a rate of about 1,000 Å/sec. and is thus unsuitable for removing polymer after the polycide gate etch. It is therefore highly desirable to have a simple and selective method for removing both sidewall polymer and the polymer veil over the photoresist layer without compromising the gate oxide or the polycide structure.
Fujimura, et. al. U.S. Pat. No. 4,983,254 show a photoresist stripping process administered in a downstream ashing reactor by adding H
2
O to a gas mixture containing O
2
and a halogen bearing species. The H
2
O suppresses the oxide etch rate but also suppresses the ashing rate. The added H
2
O removes fluorine atoms before they reach the oxide, thereby lowering the oxide etch rate. The number of oxygen atoms participating in the ashing is increased by the removal of the halogen atoms. The method is a single flow process step whereby oxide etch rate, ashing rate and ashing temperature are balanced to achieve an optimal low temperature high ashing rate with minimal oxide loss. It is not known whether this process can remove the veil polymer on photoresist exposed to HBr etching. However, because the process is relatively inflexible it is not a good candidate for cleaning thin gate oxides after polycide etch.
SUMMARY OF THE INVENTION
It is an object of this invention to provide an improved method for removing photoresist and polymer residues from the surface of an integrated circuit wafer after a plasma etch of a gate electrode structure with minimal plasma damage and minimal loss of gate oxide. The polymer residues comprise sidewall polymer and a veil polymer formed over the surface of the residual photoresist.
It is another object of this invention to provide a method for removing photoresist and polymer residues from the surface of an integrated circuit wafer by an entirely dry etching procedure.
It is yet another object of this invention to provide a method for removing photoresist and polymer residues from the surface of an integrated circuit wafer after plasma etch of a gate electrode over a gate oxide under 100 Å thick.
These objects are accomplished by ashing said photoresist and residual polymers in a plasma asher capable of soft etching using a sequence of in-situ etch steps in O
2
/N
2
and O
2
/fluorocarbon mixtures at a single temperature. Soft etching in the context used by this invention means that the sheath voltage of the plasma is kept low and the ion density in the plasma is high. This is accomplished by supplying energy to the plasma and to the substrate by independent means. Such conditions are attainable in ICP(inductively coupled plasma) and HDP(high density plasma) reactors. Under these conditions ion bombardment of the wafer is minimized while a workable ashing rate can be achieved.
Alternately, these objects may also be accomplished in the same plasma reactor by using a plasma containing O
2
, N

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