Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-10-05
2001-01-23
Le, Vu A. (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
Reexamination Certificate
active
06177316
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to electrically erasable and programmable read-only memory (EEPROM) technology. More particularly, to an improved method of fabricating NAND devices having floating gates.
BACKGROUND OF THE INVENTION
A conventional core cell in a NAND array memory device is described with reference to
FIGS. 1A and 1B
, which are simplified cross sectional diagrams of the conventional NAND array
10
having a floating gate memory cell
12
. The memory cell
12
is a floating gate transistor having a control gate
14
separated from a polycrystalline silicon floating gate
16
by an upper insulating layer while floating gate
16
is separated from a substrate
18
by a lower insulating layer. The substrate includes n+ source regions
20
, a p-doped body region
22
, and an n+ drain region
24
as in a conventional NMOS enhancement mode transistor.
As illustrated in
FIG. 1A
, in order to program the conventional floating gate memory cell
10
, control gate
14
is biased at a relatively high voltage of approximately 20 volts while body region
22
is rounded. The high voltage on the control gate
14
induces electrons from body region
22
to tunnel through the lower insulation layer and into floating gate
16
through a conventionally known process called Fowler-Nordheim tunneling. The floating gate
16
accumulates negative charge thereby increasing the threshold voltage of memory cell
12
. As illustrated in
FIG. 1B
, erasing occurs by biasing the body region
22
at a high voltage of approximately 20 volts while the control gate
14
is grounded causing the electrons from floating gate
16
to tunnel through the lower insulation layer and into the body region
22
. A NAND EEPROM based non-volatile flash memory architecture is described in U.S. Pat. No. 5,568,420, filed Nov. 30, 1994, which is herein incorporated by reference for all purposes.
Generally, a conventional NAND memory cell device, as described above, is a high density device subject to high voltage requirements. Although, the high density, high voltage characteristics are desirable traits in a NAND cell structure, these traits tend to make bit line to bit line isolation within the NAND structure more difficult. Specifically, since there is usually not enough margin for isolation between bit lines in the NAND array structure, the outdiffusion of impurities may result in low junction breakdown and bit line to bit line leakage.
Therefore, what is desired is an improved method for fabricating the NAND array structure which improves the reliability of the NAND memory cell structure by minimizing outdiffusion.
SUMMARY OF THE INVENTION
The present invention provides an improved method for fabricating a NAND-type memory cell structure. To improve the conventional NAND-type memory cell fabrication process, described in detail below, the present invention forgoes providing the contact mask implantation process prior to deposition of the metal barrier layer, which is a typical order of processing the NAND-type memory cell. Instead, in the present invention, the metal barrier layer is deposited on a core area of the NAND-type memory cell prior to contact mask implantation. Thereafter, the contact mask implantation process is performed on the structure in a conventional manner.
Accordingly, the dopant from the contact mask process concentrates itself at the Ti/Si interface, thus, minimizing the outdiffusion of impurities which is typical of NAND array structures fabricated using the conventional method of implanting directly into silicon. The improved fabrication process improves the performance and reliability of the NAND array structure by minimizing outdiffusion of impurities. The minimization of outdiffusion reduces the potential for bit line to bit line leakage and low junction breakdown.
In one aspect of the present invention, a method is provided for fabricating a memory structure. The method includes forming a metal barrier layer on a core area of a memory structure; and thereafter, performing a contact implantation process on said memory structure to reduce impurity outdiffusion. The core area includes a portion of NAND-type core memory cell structure.
The present invention being better understood upon consideration of the detailed description below, in conjunction with the accompanying drawings.
REFERENCES:
patent: 4811078 (1989-03-01), Tigelaar et al.
patent: 5229311 (1993-07-01), Lai et al.
patent: 5427963 (1995-06-01), Richart et al.
patent: 5429975 (1995-07-01), Sheu et al.
patent: 5488009 (1996-01-01), Hsue et al.
patent: 5516713 (1996-05-01), Hsue et al.
patent: 5581504 (1996-12-01), Chang
patent: 5760475 (1998-06-01), Cronin et al.
patent: 5830789 (1998-11-01), Lien et al.
patent: 5846863 (1998-12-01), Lee et al.
patent: 5972179 (1999-10-01), Chittipeddi et al.
Chang Kent K.
He Yue-Song
Wang John J.
Advanced Micro Devices , Inc.
Le Vu A.
Lopez Theodore P.
Skjerven Morrill & MacPherson LLP
Wilson Christian D.
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