Porous silicon oxycarbide integrated circuit insulator

Details Porous silicon oxycarbide integrated circuit insulator Porous silicon oxycarbide integrated circuit insulator

2001-07-20

2004-10-12

Guerrero, Maria (Department: 2822)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

C438S623000, C438S780000, C438S781000, C438S931000

Reexamination Certificate

active

06803326

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
This invention relates generally to integrated circuits, and particularly, but not by way of limitation, to a low dielectric constant porous silicon oxycarbide integrated circuit insulator for providing electrical isolation between interconnection lines and other integrated circuit components.
BACKGROUND OF THE INVENTION
Integrated circuits (IC's) typically include transistors and other circuit elements that are conductively interconnected in particular circuit configurations to provide desired circuit functions. Particular circuit elements and interconnection lines must be electrically isolated from other circuit elements and interconnection lines for proper IC operation. Modern IC technology includes insulating isolation layers. Such insulating isolation layers may be formed between transistors, between interconnection lines formed simultaneously, between interconnection lines formed as separate layers, between transistors and overlying interconnection lines, and as a passivation layer protecting underlying circuit elements and interconnection lines.
Good IC insulators should provide, among other things, low leakage currents, good mechanical strength, and low permittivity. In particular, a low permitivitty insulator (also referred to as having a low relative or absolute dielectric constant) presents reduced parasitic capacitance between circuit nodes. Since parasitic capacitance between circuit nodes increases noise coupling and signal crosstalk between circuit nodes, increases power consumption, slows circuit operation, and potentially introduces timing faults, the parasitic capacitance associated with insulating IC isolation layers should be minimized.
Trends in modern semiconductor technology are increasing the importance of minimizing the parasitic capacitance of IC isolation layers. Consumers demand high speed operation of computer and memory IC's. Battery powered portable computer and communications devices demand low power consumption for prolonged operation between battery recharges. Portability also requires more dense circuits so that more functionality can be provided in a smaller product. As circuits become more dense, interconnection lines are more closely spaced, making signal crosstalk between circuit nodes a greater concern. IC isolation layers that minimize parasitic capacitance are essential to continued advancement in semiconductor technology.
One popular IC insulator, silicon dioxide (SiO
2
) has a relative dielectric constant (&egr;
r
) of approximately 4.0. A smaller relative dielectric constant reduces the parasitic capacitance between circuit nodes. Ideally, the relative dielectric constant of an IC isolation layer should be reduced such that it approaches the relative dielectric constant of air (&egr;
r
=1). Previous attempts to minimize parasitic capacitance have included forming air-gap dielectric structures having a relative dielectric constant approaching the relative dielectric constant of air (&egr;
r
=1). Air-gap structures, however, tend to lack the mechanical strength needed to support overlying interconnection and isolation layers of high physical integrity. For the reasons stated above, and for other reasons that will become apparent upon reading the following detailed description of the invention, there is a need for providing a low dielectric constant IC insulator having better mechanical strength.
SUMMARY OF THE INVENTION
The present invention provides, among other things, a low dielectric constant IC insulator formed of porous silicon oxycarbide. In one embodiment, the invention includes an integrated circuit formed on a substrate. A plurality of transistors is formed on the substrate. A patterned first conductive layer interconnects ones of the transistors. A porous silicon oxycarbide layer insulates portions of the first conductive layer from the transistors. In another embodiment, the invention includes an integrated circuit having a porous silicon oxycarbide layer overlying the circuit elements for protecting the physical integrity of the circuit elements.
Another aspect of the present invention provides a method of fabricating an integrated circuit. A working surface of a semiconductor substrate is coated with a mixture of oxide and carbon sources. The mixture of oxide and carbon sources is heated and dried such that the mixture of oxide and carbon sources is transformed into an insulator layer on the integrated circuit. In one embodiment, the mixture of oxide and carbon sources includes polymeric precursors such as substituted alkoxysilanes. In another embodiment, the substituted alkoxysilanes are mixed with silicon alkoxides. In a further embodiment, the mixture of oxide and carbon sources includes methyldimethoxysilane (MDMS) and tetraethoxysilane (TEOS). In another embodiment, heating and drying the mixture of oxide and carbon sources comprises pyrolyzing the mixture of oxide and carbon sources.
The low dielectric constant porous silicon oxycarbide insulator provides electrical isolation, such as between circuit elements, between interconnection lines, between circuit elements and interconnection lines, or as a passivation layer overlying both circuit elements and interconnection lines. The low dielectric constant porous silicon oxycarbide insulator of the present invention reduces the parasitic capacitance between circuit nodes. As a result, the porous silicon oxycarbide insulator advantageously provides reduced noise and signal crosstalk between circuit nodes, reduced power consumption, faster circuit operation, and minimizes the risk of potentially introducing timing faults. Other advantages will also become apparent upon reading the following detailed description of the invention.


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