Polysilicon thin film transistor with a self-aligned LDD...

Details Polysilicon thin film transistor with a self-aligned LDD... Polysilicon thin film transistor with a self-aligned LDD...

2002-02-25

2002-11-05

Chaudhuri, Olik (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S197000, C438S585000, C438S586000

Reexamination Certificate

active

06475843

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a polysilicon thin film transistor (poly-Si TFT) and, more particularly, to a poly-Si TFT with a self-aligned LDD.
2. Description of the Related Art
Polysilicon thin film transistors (poly-Si TFTs) have been widely used in active matrix liquid crystal display (AMLCD) and static random access memory (SRAM) applications. One of the major problems of these TFTs is the OFF-state leakage current, which causes charge loss in LCDs and high standby power dissipation in SRAMs. Seeking to solve this problem, conventional lightly doped drain (LDD) structures have been used to reduce the drain field, thereby reducing the leakage current.
FIGS. 1A and 1B
are cross-sectional diagrams showing a conventional method of forming an LDD structure on a poly-Si TFT. As shown in
FIG. 1A
, a polysilicon. layer
12
is formed on a predetermined surface of a transparent insulating substrate
10
, and then a gate insulating layer
14
is formed on the polysilicon layer
12
. Next, using a patterned photoresist layer
16
as a mask, a heavy ion implantation process is performed to form a N
+
doped region
18
on the polysilicon layer
12
, thus the N
+
doped region
18
serves as a source/drain region. As shown in
FIG. 1B
, after removing the patterned photoresist layer
16
, a gate layer
20
is patterned on the gate insulating layer
14
to cover a part of the undoped regions of the polysilicon layer
12
. Next, using the gate layer
20
as a mask, a light ion implantation process is performed to form a N
−
doped region
22
on the undoped region of the polysilicon layer
12
. The N
−
doped region
22
serves as an LDD structure and the polysilicon layer
12
underlying the gate layer
20
serves as a channel.
However, an extra photo mask is required to expose the photoresist layer
16
, thus an error of alignment easily caused by the limitation of the exposure technique may lead to a shift of the LDD structure. In addition, the gate layer
20
is required to achieve a trapezoidal profile to prevent a step-coverage phenomenon from depositing layers on the gate layer
20
in the subsequent processes, thereby the complexity of the process, the production costs and the process time are increased. Also, since the length of the channel is varied from the tapered sidewalls of the gate layer
20
, the electric performance of the channel is not reliable.
SUMMARY OF THE INVENTION
The present invention provides a poly-Si TFT with a self-aligned LDD structure to solve problems caused by conventional techniques.
The polysilicon thin film transistor (poly-Si TFT) with a self-aligned lightly doped drain (LDD) structure has a transparent insulating substrate; a buffering layer formed on the transparent insulating substrate; a polysilicon layer formed on the buffering layer and having a channel region, an LDD structure surrounding the channel region, and a source/drain region surrounding the LDD structure; a gate insulating layer formed on the polysilicon layer; a gate layer formed on the gate insulating layer and positioned over the channel region; an insulating spacer formed on the sidewall of the gate layer and positioned over the LDD structure; and a sub-gate layer formed on the insulating spacer.
The present invention also provides a method of forming the polysilicon thin film transistor with a self-aligned lightly doped drain (LDD) structure. First, a transparent insulating substrate is provided with a polysilicon layer formed on the substrate, a gate insulating layer formed on the polysilicon layer, and a gate layer patterned on the gate insulating layer. Then, using a first ion implantation process with the gate layer as a mask, a lightly doped region is formed on the polysilicon layer to surround the gate layer. Next, an insulating layer and a barrier layer are sequentially formed on the entire surface of the substrate. Next, using dry etching to remove parts of the barrier layer, the remaining part of the barrier layer is formed over the sidewall of the gate layer. Next, using wet etching to remove the insulating layer which is not covered by the remaining part of the barrier layer, the remaining part of the insulating layer is formed on the sidewall of the gate layer. Finally, using a second ion implantation process, a heavily doped region is formed on the lightly doped region which is not covered by the remaining parts of the insulating layer and the barrier layer.
Accordingly, it is a principle object of the invention to pattern the self-aligned LDD structure without an extra photo mask.
It is another object of the invention to avoid an error of alignment caused by the limitation of the exposure technique.
Yet another object of the invention is to solve the problems caused by forming the trapezoid profile of the gate layer.
It is a further object of the invention to employ the remaining part of the barrier layer as a metal shielding bump.
Still another object of the invention is to use the poly-Si TFT with the aligned LDD structure in a high frequency operating circuit application.
These and other objects of the present invention will become readily apparent upon further review of the following specification and drawings.


REFERENCES:
patent: 4988632 (1991-01-01), Pfiester
patent: 5087582 (1992-02-01), Campbell
patent: 5430320 (1995-07-01), Lee
patent: 5741722 (1998-04-01), Lee
patent: 5770498 (1998-06-01), Becker
patent: 5940698 (1999-08-01), Gardner et al.
patent: 6117739 (2000-09-01), Gardner et al.

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