Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2003-08-21
2004-10-12
Niebling, John F. (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S759000, C257S760000
Reexamination Certificate
active
06803661
ABSTRACT:
FILED OF THE INVENTION
The invention relates generally to the manufacture of semiconductor devices, and more specifically to the method for defining precise, narrow polysilicon features.
BACKGROUND OF THE INVENTION
The semiconductor industries continuing drive toward integrated circuits whose geometric features are decreasing has in turn led to the need for photolithographic techniques using shorter wavelengths in the mid and deep ultraviolet (DUV) spectrum to achieve fine features. In the process of defining very fine patterns, optical effects are often experienced which lead to distortion of images in the photoresist that are directly responsible for line width variations, and which in turn can compromise device performance.
Many of the optical effects can be attributed to reflectivity of the underlying layers of materials, such as polysilicon and metals, which can produce spatial variations in the radiation intensity in the photoresist, and in turn result in non-uniform line width development. Radiation can also scatter from the substrate and photoresist interfaces into areas where exposure is not intended, again resulting in line width variation.
As the wavelength of exposure sources is shortened to bring improved resolution by minimizing diffraction limitations, the difficulty in controlling reflections is increased. In an attempt to circumvent the reflection problems, a number of antireflective coatings (ARC) to be interposed between the substrate and photoresist have been developed, largely for specific applications, and with varying shortcomings.
To further complicate the problem, photoresists for short wavelength exposure sources to deep ultraviolet (DUV) light are necessarily very thin, and either do not withstand, or are undercut during the etch process resulting in further deterioration of the line resolution. Clean-up and removal of both the resist, and the antireflective coating can present additional problems in the manufacturing process of sub-micron features.
As lithography moves to the 193 nm (nanometer) wavelength of an ArF excimer laser light, a need exists for a method to form sub-micron integrated circuit patterns which overlay varying topography, and often highly reflective substrate materials. In particular, defining precise, sub-micron features in relatively thick doped and undoped polysilicon over gate oxide presents a significant challenge to the industry. An inorganic antireflective coating of silicon oxynitride (SixOyNz) has been used in the industry, and while it has advantages, its selectivity to oxide, and slow removal rate with phosphoric acid post etch clean-up has an adverse effect on the polysilicon line definition, and may result in damage to active areas. Alternately, a bilayer of silicon oxynitride over doped silicon oxide has been proposed. However, the optical properties of the oxide have a narrow process window, an undesirable feature for volume manufacturing, and further the process is complicated by the requirement for a special tool for removal.
Therefore, an anti-reflective coating for deep uv exposure in the 193 nm wavelength region which is compatible with polysilicon etch and clean-up processes, and which supports volume manufacturing requirements of sub-micron polysilicon features is clearly needed by the industry.
SUMMARY OF THE INVENTION
It is an objective of the present invention to provide a method for accurately defining sub-micron polysilicon features on a semiconductor device using 193 nm wavelength lithography.
It is further an object of this invention to provide an dual layer coating which serves both as an in situ etch mask, and as a low reflectivity coating for deep UV exposure.
It is an object of the invention to provide an inorganic coating having reflectivity of less than 1% at 193 nm wavelength exposure.
It is an object of the invention to provide a method for improved lithographic depth of focus as a result of compatibility with thin photoresist and antireflective properties of the ARC.
It is an object of this invention to provide a low reflectivity hard mask for polysilicon processing having a large film thickness window.
It is an object of the invention to provide a coating comprising multiple layers wherein the thickness, the extinction coefficient and index of refraction are matched to predict, and minimize reflectivity.
It is an object of this invention to provide a hard mask which is compatible with phosphoric acid post polysilicon etch clean-up without deterioration of underlying oxide and/or active areas.
These and other objectives will be met by sandwiching between the polysilicon and photoresist layers, an ARC (anti-reflective coating) bilayer wherein the materials have matched index of refraction (n) and extinction coefficient (k) specifically to minimize reflection to less than 1% with 193 nm wavelength exposure, and which is subsequently patterned to serve as an etch hard mask. Preferably the ARC mask consists of a bottom layer of greater than 300 angstroms, and less than 1500 angstroms of silicon rich silicon nitride having an extinction coefficient of from 0.77 to 1.07, and a top layer of about 250 angstroms of silicon oxynitride having an extinction coefficient of about 0.32. The silicon nitride is in direct contact with a polysilicon layer overlying a gate oxide, or other dielectric layer. An etch hard mask is formed from the ARC bilayer by etching in selected areas unprotected by photoresist. The resist is removed by plasma ashing, and the exposed polysilicon etched along with the silicon oxynitride layer, leaving only the silicon nitride to be removed by a phosphoric acid post polysilicon etch clean-up, which does not damage active moat and gate areas.
These and other features and advantages of the present invention will become apparent from the following description which is to be read in connection with the accompanying drawings.
REFERENCES:
patent: 6013582 (2000-01-01), Ionov et al.
patent: 6537918 (2003-03-01), Ionov et al.
patent: 6720256 (2004-04-01), Wu et al.
Gross Cameron
Joseph Eric A.
Laaksonen Reima T.
Thakar Gautam V.
Brady III W. James
Lindsay Jr. Walter L.
Niebling John F.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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