Polymer memory device with electron traps

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C257S296000, C257S311000, C257S314000, C257SE21208, C438S253000, C438S393000, C438S508000

Reexamination Certificate

active

10816259

ABSTRACT:
An embodiment of the invention reduces damage caused to a polymer ferroelectric layer in a polymer ferroelectric memory device by creating excess holes in the insulating metal nitride and/or metal oxide layers between the metal electrodes and polymer ferroelectric layer. The excess holes in the metal nitride and/or metal oxide trap electrons injected by the metal electrodes under AC bias that would otherwise damage the polymer ferroelectric layer.

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patent: WO 03/003377 (2003-01-01), None
Kuo, Y., et al., “Tantalum Nitride Interface Layer Influence on Dielectric Properties of Hafnium Doped Tantalum Oxide High Dielectric Constant Thin Films”, Japanese Journal of Applied Physics, vol. 42, No. 7A, Part 2, Jul. 1, 2003, pp. L769-L771.
PCT Search Report and Written Opinion dated Apr. 7, 2006 for International Application No. PCT/US2005/010921, filed Mar. 31, 2005 (12 pages).

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