Electricity: conductors and insulators – Boxes and housings – Hermetic sealed envelope type
Reexamination Certificate
2002-08-08
2004-02-24
Reichard, Dean A. (Department: 2831)
Electricity: conductors and insulators
Boxes and housings
Hermetic sealed envelope type
C257S738000, C257S734000
Reexamination Certificate
active
06696644
ABSTRACT:
FIELD OF THE INVENTION
The present invention is related in general to the field of electronic systems and semiconductor devices and more specifically to the field of plastic packages attached to boards by solder balls, wherein an auxiliary plastic layer between the solder balls enhances the temperature cycling reliability of the plastic package.
DESCRIPTION OF THE RELATED ART
The structure of contact pad metallizations and solder bumps for connecting integrated circuit (IC) chips to semiconductor packages or outside parts, as well as the thermomechanical stresses and reliability risks involved, have been described in a series of detailed publications by the International Business Machines Corporation in 1969 (IBM J. Res. Develop., Vol. 13, pp. 226-296).
During and after assembly of the IC chip to an outside part such as a substrate or circuit board by solder reflow, and then during device operation, significant temperature differences and temperature cycles appear between semiconductor chip and the substrate. The reliability of the solder joint is strongly influenced by the coefficients of thermal expansion of the semiconductor material and the substrate material. For example, there is more than one order of magnitude difference between the coefficients of thermal expansion of silicon and FR-4. This difference causes thermomechanical stresses, which the solder joints have to absorb. Detailed calculations, in the literature cited above and in other publications of the early 1980's, involving the optimum height and volume of the solder connection and the expected onset of fatigue and cracking proposed a number of solder design solutions.
The fabrication methods and reliability problems involving flip-chips re-appear in somewhat modified form for ball-grid array type packages. In their book “Chip Scale Package” (McGraw-Hill, 1999), John H. Lau and Shi-Wei Ricky Lee describe various semiconductor devices and packages of contemporary “chip-scale” families, as they are fabricated by a number of semiconductor companies worldwide. The newest designs and concepts in microelectronics assembly and packaging are aiming for a package with a planar area not substantially greater than the silicon chip itself, or at most 20% larger area. This concept, known as Chip-Scale Package (CSP), is finding particular favor with those electronics industries where the product size is continually shrinking such as cellular communications, pagers, hard disk drivers, laptop computers and medical instrumentation. Most CSP approaches are based on assembly with solder bumps or solder balls on the exterior of the package, to interface with system or wiring boards.
The ball grid array or CSP may be attached directly to a printed circuit board (PCB), or alternatively, coupled to a second interconnection surface such as an interposer. In the latter case, attaching the ball grid array to the next interconnect is carried out by aligning the solder bumps or balls on the package to contact pads on the second level interconnection and then performing a second solder reflow operation. During the reflow, the bumps or balls liquefy and make a bond to the next interconnect level which has pads or traces to receive the solder. Following the solder reflow step, a polymeric underfill is often used between the package and the interposer (or PCB) to alleviate mechanical stress caused by the mismatch in the coefficients of thermal expansion (CTE) between the package, the interposer, if any, and the PCB. Many reliability problems occur due to the stress placed on the solder bumps or balls when the assembly is cycled from hot to cool during operation.
One method of drastically reducing the thermomechanical stress on the solder bumps has been utilized in Tessera's Micro-Ball Grid Array packages. A sheet-like compliant elastomer substantially de-couples the solder bumps, affixed to the outside PCB, from the IC chip and the interposer, thus relieving the thermal mismatch. Among the drawbacks of this method are assembly hurdles and cost considerations.
Another method aims at absorbing part of the thermomechanical stress on the solder joints by plastic material surrounding the joints and filling the gap between chip and substrate. See for instance, U.S. Pat. No. 6,228,680, issued on May 8, 2001; U.S. Pat. No. 6,213,347, issued on Apr. 10, 2001, and U.S. Pat. No. 6,245,583, issued on Jun. 12, 2001 (Thomas et al. , Low Stress Method and Apparatus for Underfilling Flip-Chip Electronic Devices). However, the underfilling method represents an unwelcome process step after device attachment to the motherboard.
In a recent wafer-level process approach by Kulicke & Soffa, flux-impregnated epoxy is screened on the wafer, with openings for the chip contact pads. The solder balls are placed on the pads; during the reflow process, the epoxy softens and forms a fillet at the base of the solder ball. An epoxy “collar” extends about 50 to 100 &mgr;m up the side of the solder ball from the chip surface, where stress-induced cracks typically originate. This collar restricts the creep flow of the solder, where cracks typically form. The wafer-level process with the required high temperature of solder reflow cannot be transferred to individual plastic packages. As another drawback, the adhesion between the solder balls and the plastic fillet is weak at best and often non-existent.
An urgent need has arisen for a coherent, low-cost method of preventing stress-induced solder bump cracks during temperature cycling for ball-grid array packages. The method should be flexible enough to be applied for different semiconductor product families and a wide spectrum of plastic package design and process variations. Preferably, these innovations should be accomplished using the installed equipment base so that no investment in new manufacturing machines is needed.
SUMMARY OF THE INVENTION
A plastic package for use in semiconductor devices is described, which has a plurality of metallic terminals exposed on a package surface and a metallic bump attached to each of said terminals. The bumps are made of reflowable metal and have approximately uniform height. An adherent layer of polymer material covers the package surface and surrounds each of the bumps to form a solid meniscus. The layer has a thickness between a quarter and one half of the bump height. An analogous methodology applies to plastic assembly boards.
In the method for completing a polymer plastic package according to the invention, the solder bumps are attached and reflowed first, resulting in an approximately uniform predetermined height. Then, a water-soluble polymer is stencil-printed to coat the top surface of the bumps. In a vacuum chamber, an energy-controlled plasma roughens and cleans the polymer surface, improving the surface affinity to adhesion. An adherent polymeric precursor is distributed between and around the bumps to form a meniscus on each of the bumps and fill the space between the bumps with a layer having a thickness between a quarter and one half of the height of the bumps. Additional thermal energy cures the polymeric precursor, solidifying the layer and the meniscus. Finally, DI water removes the water-soluble polymeric bump coating.
Detailed model calculations as well as experimental data show that the polymer coat on plastic packages, applied by the method of the invention, reduces the plastic energy density by 50% and increases the board-level reliability in temperature cycling from −40 to +125° C. by 50% compared to standard plastic packages.
It is an aspect of the present invention to provide a flexible methodology of fabrication and material selection to achieve the benefit of the stress-relieving polymer coat.
Another aspect of the invention is to provide a methodology for a wide range of plastic ball-grid array and chip-scale packages.
It is a technical advantage of the present invention that a wide variety of solder alloys and reflow temperatures can be employed for the stress-reduced packages.
Another technical advantage is the possibility to apply the
Chiu Tz-Cheng
Variyam Manjula N.
Brady III Wade James
Nino Adolfo
Reichard Dean A.
Shrehot Michael K.
Telcky, Jr. Frederick J.
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