Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Self-aligned
Reexamination Certificate
2002-04-09
2003-11-11
Zarabian, Amir (Department: 2822)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Self-aligned
C438S340000, C438S338000, C438S369000, C438S548000, C438S533000, C438S546000, C438S979000, C438S983000
Reexamination Certificate
active
06645820
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to circuits coupled to an integrated circuit that provides protection from electrostatic discharge (ESD) events. More particularly, this invention relates to circuits that will prevent a differential voltage level between two different power supply voltage terminals from exceeding a specified voltage level and thus prevent damage to the integrated circuit.
2. Description of Related Art
Integrated circuits often have either multiple terminals connected to a single power supply voltage source or multiple isolated power supply voltage sources. The power supply voltage sources are connected through separate distribution networks to the internal integrated circuits. The structure of the internal integrated circuits may have a core logic section and a peripheral logic section. In order to isolate noise, such as caused by simultaneous switching of driver circuits in the peripheral logic section or impedance mismatch on transmission line connected to an input/output (I/O) pad, the peripheral logic section would have a separate power supply distribution network from that of the core logic section. Similarly, the internal circuits may include analog circuits requiring multiple power supply voltage sources and need to be isolated from the core logic and peripheral logic section to prevent conduction of noise to the analog circuits.
While the core logic section and the peripheral logic section often have a common power supply voltage source, it is not uncommon for the core logic section to have a power supply voltage source of a different voltage level than the peripheral logic section. For instance, the peripheral logic section may have a power supply voltage source of 5.0V and the core logic section may have a power supply voltage source of 3.3V. It is further common that the analog section require even different voltage levels than the core logic section or the peripheral logic section. Further, the internal integrated circuits may have implementations with multiple core logic sections, multiple peripheral logic sections, and multiple analog core sections. Each section will have a separate voltage distribution network for the power source and return paths.
An ESD event is commonly a pulse of a very high voltage typically of several kilovolts with a moderate current of a few amperes for a short period, typically about 100 nanoseconds. The common source of an ESD event is bringing the integrated circuit in contact with a human body or a machine such as an integrated circuit tester and handler.
If an I/O pad is contacted and subjected to an ESD event, the power supply distribution network of the peripheral logic section connected to the I/O pad begins to change relative to the voltage level of the power supply voltage source connected to the core logic section. This change can cause damage in subcircuits that form an interface between the core logic section and the peripheral logic section.
FIG. 1
illustrates a structure of the prior art of a voltage clamping circuit employed to prevent damage between the distribution networks of two separate power supply voltage sources. The structure of
FIG. 1
illustrates a two-staged voltage clamping circuit, which may be expanded by the addition of more stages.
A substrate has the distribution networks
55
and
60
to connect the separate power supplies V
sup1
and V
sup2
to the internal circuitry
65
. To provide the protection from any ESD events, the voltage clamping circuit is connected between the distribution networks
55
and
60
to connect the separate power supplies V
sup1
and V
sup2
. The voltage clamping circuit has an N-type impurity diffused to a lightly doped level into the P-type substrate to form the N-wells
10
and
15
. The N-type impurity is diffused to a high concentration level into the N-wells
10
and
15
to form the heavily doped N-regions
20
,
25
,
35
, and
45
. A P-type material is diffused to a high concentration into the N-wells
10
and
15
to form the heavily doped P-regions
30
and
40
. Simultaneously the P-type material is diffused into the substrate
5
to form the P-region
50
. Contact metallurgy is alloyed to the P-type region
50
to form a contact that is connected to the ground reference distribution system
75
.
Contact metallurgy is alloyed to the P-type regions
30
and
40
to form contacts that are respectively connected to the distribution networks
55
and
60
for the power supply voltage sources V
sup1
and V
sup2
. Contact metallurgy is alloyed to the N-type regions
20
and
25
and to the P-type region
40
to form a contact that serially interconnects the two stages of the voltage clamping circuit. Contact metallurgy is alloyed to the N-type regions
35
and
45
to form contacts that are connected to the distribution network
60
that is connected to the power supply voltage source V
sup2
.
The diode D
1
70
a
is formed at the junction of the P-region
30
and N-well
10
in conjunction with the N-region
20
. Similarly, the diodes D
2
70
b
, D
3
70
c
, and D
4
70
d
are formed at the junction of the P-regions
30
and
40
and N-wells
10
and
15
in conjunction respectively with the N-regions
25
,
35
, and
45
. Further the emitter of the vertical PNP transistor
75
a
is formed by the P-region
30
, the base being the N-well
10
, and the collector being the P-type substrate
5
. Likewise, the emitter of the vertical PNP transistor
75
b
is formed by the P-region
40
, the base being the N-well
15
, and the collector being the P-type substrate
5
.
Referring now to
FIG. 2
for a discussion of the operation of the voltage clamping circuit of the prior art. In this example, the voltage clamping circuit has multiple PNP transistors
75
a
,
75
b
, . . . ,
75
m
, . . . ,
75
n
serially connected emitter to base. The emitter of first PNP transistor
75
a
is connected to the distribution network
55
of the power supply voltage source V
sup1
. The base of the last PNP transistor
75
n
is connected to the distribution network
60
of the power supply voltage source V
sup2
. The collectors of the PNP transistors
75
a
,
75
b
, . . . ,
75
m
, . . . ,
75
n
are connected to the ground reference distribution system
75
. If the voltage level present on the distribution network of the power supply voltage supply V
sup1
increases to a threshold level greater than the voltage level of the power supply voltage source V
sup2
, the base-emitter diodes of the PNP transistors
75
a
,
75
b
, . . .
75
m
, . . . ,
75
n
begin to conduct to clamp any voltage difference between the power supply voltage source V
sup1
and the power supply voltage source V
sup2
to maintain the threshold level difference between the power supply voltage sources V
sup1
and V
sup2
.
The threshold level is determined by the number of serially connected PNP transistors
75
a
,
75
b
, . . . ,
75
m
, . . . ,
75
n
and is calculated from the formula:
V
t
=mV
d
−V
o
m*m
(
m
−1)*
ln(&bgr;+1)/2
where:
V
t
is threshold level of the voltage clamping circuit.
m is the number of PNP transistors
75
a
,
75
b
, . . . ,
75
m
, . . . ,
75
n.
V
d
voltage developed across each individual base emitter junction of the PNP transistors
75
a
,
75
b
,
75
m
, . . . ,
75
n.
V
o
is determined by the formula:
V
o
=
KT
q
where:
K is Boltzman's constant.
T is the temperature.
q is electrical charge of an electron.
It is known that the main cause in a decrease in the breakdown or conduction voltage of during an ESD event is the leakage current from of the base-emitter junction of the PNP transistors
75
a
,
75
b
, . . . ,
75
m
, . . . ,
75
n
. Thus, as the number of PNP transistors
75
a
,
75
b
, . . . ,
75
m
, . . . ,
75
n
increases, the threshold level does not increase concomitantly.
Other ESD device structures as illustrated in U.S. Pat. No. 5,674,761 (Chang, et al.), U.S. Pat. No. 5,856,214 (Yu), and U.S. Pat. No. 6,096,584 (Ellis-Monaghan, et al.) provide ESD devices structures that prevent dama
Chen Shui-Hung
Lee Jian-Hsing
Peng Kuo Reay
Ackerman Stephen B.
Guerrero Maria
Saile George O.
Taiwan Semiconductor Manufacturing Company
Zarabian Amir
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