Polycide gate structure and method of manufacture

Details Polycide gate structure and method of manufacture Polycide gate structure and method of manufacture

2000-08-15

2002-12-10

Dang, Trung (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S595000, C438S596000

Reexamination Certificate

active

06492250

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor structure and method of manufacture. More particularly, the present invention relates to a polycide gate structure and method of manufacture.
2. Description of Related Art
As dimensions of semiconductor devices continue to shrink, electrical resistance of interconnecting lines will increase. To reduce electrical resistance, a silicide layer is normally deposited over the polysilicon gate in most MOS manufacturing processes to form a polycide gate structure.
FIG. 1
is a schematic cross-sectional view showing a conventional polycide gate structure. To form a conventional polycide gate, a gate dielectric layer
110
, a conformal polysilicon layer
120
, a silicide layer
130
, a silicon nitride layer
140
and a patterned photoresist layer
150
are sequentially formed over a substrate
100
. Using the patterned photoresist layer
150
as a mask, an anisotropic etching operation is carried out to etch the silicon nitride
140
, the silicide layer
130
and the polysilicon layer
120
sequentially to form the polycide gate. The silicon nitride layer
140
serves as a cap layer in a subsequent self-aligned contact process. In the etching step, HBr/Cl
2
plasma
170
is often used for etching the polysilicon layer
120
. In general, chlorine plasma (Cl
2
) is rarely used alone because serious undercutting of the polysilicon layer
120
may occur resulting in poor quality. On the other hand, if hydrogen bromide (HBr) plasma is used alone, line width of gates in different areas of a wafer may be affected leading to a variation in the electrical properties of devices. Etching with HBr/Cl
2
plasma is able to prevent both undercutting and line width problems.
However, when the polysilicon layer
120
is etched using HBr/Cl
2
plasma
170
, the sidewalls of the silicide layer
130
above the polysilicon layer
120
may be attacked by highly reactive Cl
2
plasma. Ultimately, recesses
135
may form due to the undercutting of the silicide layer
130
.
FIG. 2
is a schematic cross-sectional view showing an improved version of a conventional gate polycide structure. The newer version is able to prevent the undercutting of the silicide layer when the polysilicon layer is etched. To form the gate structure as shown in
FIG. 2
, a gate dielectric layer
210
, a conformal polysilicon layer
220
, a silicide layer
230
, a silicon nitride layer
240
and a patterned photoresist layer
250
are sequentially formed over a substrate
200
. The photoresist layer
250
has a width L. Using the photoresist layer
250
as a mask, an anisotropic etching operation is carried out to etch the silicon nitride layer
240
and the silicide layer
230
in sequence. The exposed polysilicon layer
220
is etched using HBr/Cl
2
plasma with CF
4
or C
2
F
6
molecules therein to form a polycide gate
280
. The presence of CF
4
or C
2
F
6
molecules in the plasma will result in a carbon chain polymerization. Hence, a protective polymer layer
260
is formed over the sidewalls of the silicide layer
230
, the silicon nitride layer
240
and the patterned photoresist layer
250
. Hence, corrosion of the silicide layer
230
is prevented. However, thickness of the protective polymer layer
260
in various locations within the wafer is difficult to control. Consequently, fabricating a polysilicon layer
220
of width L just underneath the silicide layer
230
is difficult to do with precision, leading to a deterioration of device properties. In addition, the additives CF
4
and C
2
F
6
are not quite suitable for etching polysilicon layer
220
when a silicon nitride layer is used as a hard mask. This is because CF
4
and C
2
F
6
plasma has a high etching rate for silicon nitride. Consequently, too much silicon nitride may be removed from the silicon nitride layer
240
. Ultimately, subsequent process for forming a self-aligned contact may be affected.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a method of forming a polycide gate. A substrate having a gate dielectric layer, a polysilicon layer, a silicide layer and an insulation layer thereon is provided. The polysilicon layer is formed above the gate dielectric layer, the silicide layer is formed above the polysilicon layer, and the insulation layer is formed above the silicide layer. A patterned photoresist layer is formed over the insulation layer. Using the photoresist layer as a mask, an anisotropic etching operation is carried out to remove the exposed insulation layer. Again using the photoresist layer as a mask, a first type of plasma is used to carry out a first anisotropic etching operation to remove the exposed silicide layer. A metallic oxide layer is formed on the sidewalls of the silicide layer by the oxidation of a portion of the retained silicide layer. Using the photoresist layer as a mask, a second type of plasma is used to carry out a second anisotropic etching operation to remove the exposed polysilicon layer. The metallic oxide layer is resistant to attack by the second type of plasma.
In addition, the method of forming a polycide gate in this invention further includes removing the photoresist layer after the first anisotropic etching step. Hence, the patterned insulation layer becomes the hard mask layer in the second anisotropic etching step.
This invention utilizes the formation of a metallic oxide layer on the sidewalls of the silicide layer after the first anisotropic etching step. Hence, the silicide layer is protected from reactive components inside the second type of plasma by the metallic oxide layer when the polysilicon layer is etched in the second anisotropic etching step. In other words, undercutting of the silicide layer is prevented. Furthermore, since no additives such as CF
4
and C
2
F
6
molecules are added to the reactive plasma in the polysilicon etching operation, thickness variation in protective polymer layer across the wafer no longer presents a problem. Moreover, even if an insulation layer fabricated from silicon nitride material is used as an etching hard mask, loss of insulation material no longer presents a problem for forming self-aligned contacts in a subsequent operation.
This invention also provides a polycide gate structure. The polycide gate structure is formed by the aforementioned method. The structure is formed on a substrate having a gate dielectric layer thereon. The polycide gate structure includes a patterned polysilicon layer, a silicide layer, a metallic oxide layer and an insulation layer. The polysilicon layer is above the gate dielectric layer. The silicide layer is above the polysilicon layer. The metallic oxide layer is on the sidewalls of the silicide layer. The metallic element within the metallic layer is identical to the metallic element within the silicide layer. The insulation layer is above the silicide layer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5368686 (1994-11-01), Tatsumi et al.
patent: 5698072 (1997-12-01), Fukuda
patent: 6001718 (1999-12-01), Katata et al.
patent: 6017809 (2000-01-01), Inumiya et al.
patent: 6162717 (2000-12-01), Yeh
patent: 6177334 (2001-01-01), Chen et al.
“Control of sidewall deposition and profile in Ti-polycide tching” M. Nagase, E. Soda, K. Yosbida, and N. Aoto / 1999, Dry Process Symposium / p. 127-132.

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