Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1998-11-17
2000-09-12
Smith, Matthew
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438257, 438299, 257288, 257314, H01L 21336, H01L 2972, H01L 3100
Patent
active
061177334
ABSTRACT:
A novel method of forming a first polysilicon gate tip (poly tip) for enhanced F-N tunneling in split-gate flash memory cells is disclosed. The poly tip is further enhanced by forming a notch in two different ways in a nitride layer overlying the first polysilicon layer. In one embodiment, the notch is formed after wet oxidizing the sidewalls of the underlying first polysilicon layer, thus at the same time forming a poly tip which is exposed upwardly but covered by polyoxide on the side. In another embodiment, the notch is formed prior to the oxidation of the exposed regions of the first polysilicon layer, such as the sidewalls, so that during the subsequent oxidation, not only the sidewalls but also the exposed portions of the polysilicon in the notch region are also oxidized. Because the oxidation of the polysilicon advances in a non-uniform manner with very little at the polysilicon
itride interface and to a larger rate elsewhere, a thin and robust polysilicon tip is formed which is at the same time covered by oval-shaped poly-oxide on all sides. A method of forming a self-aligned source (SAS) line is also disclosed in conjunction with the forming of the polytip. Hence the combination of an enhanced poly tip with a self-aligned source provides a faster split-gate flash memory device.
REFERENCES:
patent: 5045488 (1991-09-01), Yeh
patent: 5095344 (1992-03-01), Harari
patent: 5262655 (1993-11-01), Ashida
patent: 5270240 (1993-12-01), Lee
patent: 5278087 (1994-01-01), Jenq
patent: 5408130 (1995-04-01), Woo et al.
patent: 5455792 (1995-10-01), Yi
patent: 5494838 (1996-02-01), Chang et al.
patent: 5554564 (1996-09-01), Nishioka et al.
patent: 5572054 (1996-11-01), Wang et al.
patent: 5651859 (1997-07-01), Chan et al.
patent: 5707898 (1998-01-01), Keller et al.
patent: 5714412 (1998-02-01), Liang et al.
patent: 5783473 (1998-07-01), Sung
patent: 5814551 (1998-09-01), Park et al.
patent: 5858844 (1999-01-01), Fang et al.
patent: 5872036 (1999-02-01), Sheu
patent: 5940706 (1999-08-01), Sung et al.
patent: 5994192 (1999-11-01), Chen
patent: 6001719 (1999-12-01), Cho et al.
S.Wolf,"Silicon Processing For The VLSI Era" vol. II, 1990, Lattice Press. Sunset Beach, CA, p632-634,438.
Hsieh Chia-Ta
Kuo Di-Son
Lin Yai-Fen
Sung Hung-Cheng
Ackerman Stephen B.
Malsawma Lex H.
Saile George O.
Smith Matthew
Taiwan Semiconductor Manufacturing Company
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