Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation
Reexamination Certificate
2001-07-10
2003-03-25
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Total dielectric isolation
C438S403000, C438S311000
Reexamination Certificate
active
06537890
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a poly-silicon (poly-Si) thin film transistor (TFT) having back bias effects and a fabrication method thereof, and more particularly, to a poly-Si TFT and a fabrication method thereof, in which a conducting underlayer or an island type buried electrode pad is formed on the lower portion of the TFT in order to apply a back bias, to thereby enhance characteristics of a leakage current, a sub-threshold slope, and an on-current, and revealing a stable operational performance.
2. Description of the Related Art
In general, a poly-crystalline thin film transistor (TFT) is used as a device for driving an active matrix liquid crystal display (LCD).
By the way, since a LCD uses glass as a substrate, it is required that a crystalline temperature for crystallizing an amorphous silicon film used as an active region into a poly-Si film be lowered.
Recently, a new method called a metal induced lateral crystallization (MILC) method has been developed as a method for crystallizing amorphous silicon deposited by a low-pressure vapor deposition method in order to fabricate a TFT at a low temperature of 500° C. or below.
When an amorphous silicon thin film is crystallized by a thermal treatment, the above method uses a silicide reaction between an amorphous silicon and a metal such as nickel (Ni), to thereby obtain an excellent poly-Si TFT of a large crystal particle under the temperature of 500° C. or below.
The above conventional poly-Si TFT fabricated by the Ni Offset and the MILC method has an excellent transistor characteristic.
However, in the result of measuring the transistor characteristic, the TFT reveals a leakage current value of ~10
−7
A/&mgr;m in the case that a gate voltage is 0V and when a drain voltage is high, that is, V
DS
>10V.
This value is a leakage current value larger by about one-thousand times as ~10
−10
A/&mgr;m which requires to drive an active matrix liquid crystal display (AM-LCD) using a poly-Si TFT.
Thus, it is essential to fabricate a transistor having a lower leakage current characteristic in order to apply a transistor fabricated by the MILC.
Also, since a voltage is not applied to a channel region of a device in the case of a transistor formed on an insulation substrate as in a poly-Si TFT, a device operational performance is degenerated.
SUMMARY OF THE INVENTION
To solve the above problems, it is an object of the present invention to provide a poly-Si TFT and a fabrication method thereof, in which a conducting underlayer is provided in the entire lower portion of a transistor when a poly-Si TFT is fabricated, and thus a transistor leakage current characteristic is enhanced by applying a back bias voltage to the TFT.
It is another object of the present invention to provide a poly-Si TFT and a fabrication method thereof, in which a buried electrode pad for applying a back bias is provided in the lower portion of a transistor channel region, and thus a transistor leakage current characteristic and a sub-threshold slope are further enhanced.
It is another object of the present invention to provide a double gate type poly-Si TFT and a fabrication method thereof, in which a buried type lower gate pad is provided in the lower portion of a transistor channel region, and thus a transistor leakage current characteristic, a sub-threshold slope and an on-current characteristic are further enhanced.
To accomplish the above object of the present invention, there is provided a method of fabricating a poly-Si TFT having back bias effects, the poly-Si TFT fabrication method comprising the steps of: (a) forming a conducting underlayer to which a back bias voltage is applied by using a conductive material on the entire surface of one side of a glass substrate; (b) forming a buffer layer by using an insulation material on the upper portion of the conducting underlayer; and (c) forming a poly-Si TFT on the upper portion of the buffer layer.
The conducting underlayer is made of either a metal thin film or an impurity doped silicon thin film. The metal film used as the conducting underlayer is preferably a molybdenum (Mo) thin film.
The buffer layer may be made of a silicon oxide film formed by an electromagnetic resonance plasma enhanced chemical vapor deposition method.
The poly-Si TFT forming step (c) comprises a step of forming an active region by crystallizing an amorphous silicon. The crystallization method is made of a metal induced lateral crystallization method (MILC) method.
Further, the present invention further comprises a step of patterning the conducting underlayer in the same manner as that of the gate pattern of the thin film transistor, to thereby form an island type buried electrode pad to which aback bias is applied. Accordingly, the back bias is locally applied to the channel region of the obtained TFT.
The poly-Si TFT forming step (c) also comprises the steps of: (c1) depositing and patterning an amorphous silicon to form an active region; (c2) depositing a gate insulation film and a conducting film on the amorphous silicon and then etching the result to form a gate and a gate insulation film; (c3) depositing a nickel layer to the position where the source region and the drain region of the transistor are positioned on the amorphous silicon layer, and injecting impurities in order to define source and drain regions; (c4) thermally treating the result after injecting the impurities and changing the amorphous silicon portion where the nickel layer is deposited into a region crystallized by a metal induced crystallization (MIC) method, and changing the portion where the impurities are injected into a region crystallized by metal induced lateral crystallization (MILC) method; and (c5) forming gate, source and drain electrodes in the gate, source and drain regions, respectively, and connecting the conducting underlayer with a back bias electrode for applying a back bias voltage (V
backbias
).
According to another aspect of the present invention, there is also provided a poly-Si TFT having back bias effects, the poly-Si TFT comprising: a glass substrate; a conducting underlayer formed of a conductive material on the entire surface of one side of the glass substrate where the back bias voltage is applied; a buffer layer formed of an insulation material on the upper portion of the conducting underlayer; and a poly-Si TFT formed on the upper portion of the buffer layer.
The TFT can increase an operational current of the transistor and reduce a leakage current by applying a negative voltage to an electrode connected to the conducting underlayer.
There is also provided a poly-Si TFT having back bias effects, the poly-Si TFT comprising: a glass substrate; an island type buried electrode pad formed of a conductive material on one side of the glass substrate where the back bias voltage is applied; a buffer layer formed of an insulation material on the entire surface of the glass substrate; and a poly-Si TFT formed on the upper portion of the buffer layer.
In this case, a negative back bias is applied to the buried electrode pad, to thereby interrupt an N-type channel from forming due to a back surface defect.
Also, an electrode is formed so that a voltage equal to the gate voltage of a TFT is applied to the buried electrode pad as a back bias, to thereby obtain a double gate TFT.
According to still another aspect of the present invention, there is also provided a double gate type TFT comprising: a glass substrate; a buried type lower gate pad for applying a back bias voltage on one side of the glass substrate; a buffer layer formed of an insulation material on the entire surface of the glass substrate; an active region formed of a poly-Si TFT on the upper portion of the buffer layer; source and drain regions which are formed on both sides of the active region, respectively; a gate oxide film formed on the upper portion of the channel region between the source and drain regions; and an upper gate formed on the upper portion of the gate oxide film, wherein an identical gate
Joo Seung Ki
Kim Ki Bum
Yoon Yeo Geon
Joo Seung Ki
Jr. Carl Whitehead
Rosenberg , Klein & Lee
Schillinger Laura M
LandOfFree
Poly-silicon thin film transistor having back bias effects... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Poly-silicon thin film transistor having back bias effects..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Poly-silicon thin film transistor having back bias effects... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3054990