Poly resistor structure for damascene metal gate

Details Poly resistor structure for damascene metal gate Poly resistor structure for damascene metal gate

2001-04-30

2002-06-18

Dang, Trung (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S185000, C438S238000

Reexamination Certificate

active

06406956

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method for the simultaneous formation of a metal gate for CMOS devices using a replacement gate process and a polysilicon resistor.
(2) Description of the Prior Art
Conventional methods of creating CMOS devices use gate electrodes of polysilicon that is deposited and patterned over a layer of gate oxide, in many applications the surface of the patterned and etched layer of polysilicon is salicided in order to meet requirements of low contact sheet resistivity. With the continued decrease in device and device feature dimensions, the polysilicon of the gate electrode is more prone to depletion of the polysilicon which results in a significant reduction in device performance. Polysilicon depletion results in increased resistivity of the layer of polysilicon, which in turn results in an increase of the voltage drop across the polysilicon gate electrode when this electrode is reverse mode biased. To address and largely negate this problem and in view of the fact that metal is a good conductor, the industry in increasingly turning to the use of metal to create gate electrodes. Metal however is susceptible to migration to surrounding regions under conditions of elevated temperature that can arise during the process of creating the CMOS device. The gate length of CMOS devices is the distance between the source and the drain regions of the device where this distance extends underneath the gate electrode. With the continued decrease in device dimensions, the gate length for sub-micron devices has been decreased to 0.25 &mgr;m or less. For such small gate length, the control of the Critical Dimension (CD) of this parameter becomes a challenge. To address this aspect of metal gate electrode design, the approach has been provided whereby a dummy gate is first created. This dummy gate uses a dielectric, such as silicon dioxide or a polymer, for the body of the gate. The area surrounding the gate electrode is shielded by the deposition of a layer of for instance oxide, an opening is created in this layer of oxide that aligns with the surface of the gate electrode after which the dummy gate is removed. The opening that is created in this manner can now be filled with new dielectrics first, for instance silicon dioxide or other high-k material, and filled with metal. Polishing of the surface of the deposited metal completes the creation of the sub-micron metal gate electrode. Critical in this process is the ability to control the end-point of the polishing step, since this end-point determines the height of the gate electrode and therefore the performance of the CMOS device.
As part of creating semiconductor devices, resistors are frequently required that have a high value of resistivity. Conventional processes create the gate electrode and the high resistivity resistor as two different steps, that is the gate electrode is typically first created after which the resistor is created. This implies a duality of processing steps that incurs unnecessary processing cost.
The prior art processing steps that are applied for the creation of a metal gate electrode will be described following. Referring to
FIG. 1
there is shown a cross section of a semiconductor surface
10
, preferably the surface of a monocrystalline silicon substrate, on the surface of which a gate electrode
12
has been created. Isolation regions
14
have been formed in the surface of surface
10
in order to define and electrically isolate active surface regions in the surface of layer
10
. After the regions
14
of for instance Field Oxide (FOX) or of Shallow Trench Isolation (STI) have been created, a layer
16
of pad oxide is created over the surface of substrate
10
by methods of either Chemical Vapor Deposition (CVD) or by exposing the surface of substrate
10
to an oxidizing environment under elevated temperatures.
After the layer
16
of pad oxide has been created, a dummy gate electrode layer
18
is formed by depositing polysilicon. Conventional methods of photolithography and anisotropic etching are applied to the layers
16
of pad oxide and
18
of polysilicon to form the patterned layers
16
and
18
that are shown in cross section in FIG.
1
.
Lightly Doped (LDD) source implant
20
and drain implant
22
are performed next that are self-aligned with the gate structure
16
/
18
and that extend laterally along the surface of substrate
10
in the immediate adjacency of the gate electrode structure
16
/
18
. Dependent on the type of device that is being created, that is a NMOS or a PMOS device, these implants are either n-type or p-type impurities. Gate spacers
24
typically have a thickness of between 300 and 2000 Angstrom.
Source region
26
and drain region
28
are next formed in the surface of substrate
10
. For NMOS devices, the implants for the source and drain regions use n-type impurities such as arsenic or phosphorous, for PMOS devices a p-type implant such as indium or boron can be used. The surface of the gate electrode structure
16
/
18
can next be salicided in order to reduce the contact resistance with the gate electrode. This saliciding of the surface of the gate electrode at the same time salicides the surface regions of the source and drain regions of the gate electrode.
Layer
30
of the gate electrode has been highlighted as being a salicided layer since the process of salicidation can be performed simultaneously with saliciding the source and drain contact points of the gate structure. For the creation of layer
30
tungsten can be applied.
Further shown in cross section in
FIG. 1
is the deposition of a blanket layer
32
over the dummy gate electrode
12
and the exposed surface of substrate
10
, thereby including the surface of the isolation regions
14
. This layer
32
of dielectric, preferably containing silicon dioxide, is deposited to a thickness such that the surface of layer
32
is at least equal to the surface of the salicided layer
30
on the surface of the dummy gate electrode
16
/
18
. Dielectric that has been deposited exceeding this height can be removed by Chemical Mechanical Polishing or by methods of etching. Layer
30
of salicided material is of higher hardness than the surface of the layer
32
of dielectric that is being polished and can therefore serve as a stop layer for the CMP process.
FIG. 2
shows the removal
34
of the dummy gate electrode comprising the layers
16
,
18
and
30
from between the gate spacers
24
, forming an opening
35
between the gate spacers
24
. The dummy gate can be removed using conventional methods of etch. The layer
16
of pad oxide can be removed using CHF3/CF4 or HF etch chemistry.
Referring now to
FIG. 3
, a layer
36
of gate dielectric is deposited over the surface of layer
32
and the inside surfaces of opening
35
that has been created between gate spacers
24
. Over the surface of the dielectric layer
36
is deposited a layer
38
of metal that is deposited to a thickness sufficient to fill opening
35
. The gate electrode can further comprise a barrier layer, copper interconnects should be encapsulated by at least one diffusion barrier to prevent diffusion into the silicon dioxide layer. Silicon nitride is a diffusion barrier to copper, the prior art teaches that copper interconnects should not lie on a silicon nitride layer because it has a high dielectric constant compared with silicon dioxide. The high dielectric constant when applied with interconnects causes an undesired increase in capacitance between the interconnects and the substrate. For the case of a metal gate electrode, a high-k dielectric is required for the metal structure making silicon nitride a desirable dielectric for copper applications.
Referring to
FIG. 4
, this cross section shows the results that are obtained by polishing layers
38
and
36
down to the surface of the layer
32
of dielectric.
The metal gate electrode that is shown. in cross section in
FIG. 4
provides a metal g

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