Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-05-08
1999-11-16
Bowers, Charles
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438588, 438692, 438225, H01L 218238
Patent
active
059857064
ABSTRACT:
A semiconductor process in which an initial gate dielectric layer is formed on an upper surface of a semiconductor substrate. The initial gate dielectric layer is polished with a chemical mechanical polish to produce a finished gate dielectric layer. A thickness of the finished gate dielectric layer is less than a thickness of the initial gate dielectric layer and the thickness of the preferred finished gate dielectric layer is in the range of approximately 25 to 60 angstroms. In one embodiment, the initial gate dielectric layer is formed by thermally oxidizing the semiconductor substrate in an oxygen bearing ambient maintained at a temperature in the range of approximately 600.degree. C. to 900.degree. C. In an alternative embodiment, the formation of the initial gate dielectric layer is achieved by depositing an oxide. In this embodiment, the deposited oxide is preferably fabricated by a chemical vapor deposition process using a TEOS source in a CVD reactor chamber maintained at a temperature in the range of approximately 300.degree. C. to 600.degree. C. and a pressure of less than approximately two torrs. In a presently preferred embodiment, the polishing includes depositing a slurry on a ceramic polishing pad and applying the gate dielectric to the polishing plate in the presence of the slurry while rotating the ceramic plate with respect to the semiconductor substrate. The slurry preferably comprises fumed silica suspended in a suspending solution. The suspending solution preferably comprises KOH or NH.sub.3 OH. In one embodiment, the polishing plate is comprised of aluminum oxide.
REFERENCES:
patent: 5663086 (1997-09-01), Rostoker et al.
patent: 5866458 (1999-02-01), Lee
Gardner Mark I.
Gilmer Mark C.
Advanced Micro Devices , Inc.
Bowers Charles
Daffer Kevin L.
Lee Hsien-Ming
LandOfFree
Polishing method for thin gates dielectric in semiconductor proc does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Polishing method for thin gates dielectric in semiconductor proc, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Polishing method for thin gates dielectric in semiconductor proc will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1323993