Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2005-10-25
2005-10-25
Dang, Phuc T. (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S593000, C438S959000
Reexamination Certificate
active
06958272
ABSTRACT:
A technique for forming at least part of an array of a dual bit memory core is disclosed. Initially, a portion of a charge trapping dielectric layer is formed over a substrate and a resist is formed over the portion of the charge trapping dielectric layer. The resist is patterned and a pocket implant is performed at an angle to establish pocket implants within the substrate. A bitline implant is then performed to establish buried bitlines within the substrate. The patterned resist is then removed and the remainder of the charge trapping dielectric layer is formed. A wordline material is formed over the remainder of the charge trapping dielectric layer and patterned to form wordlines that overlie the bitlines. The pocket implants serve to mitigate, among other things, complementary bit disturb (CBD) that can result from semiconductor scaling. As such, semiconductor devices can be made smaller and increased packing densities can be achieved by virtue of the inventive concepts set forth herein.
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Solid Sate Technology's WaferNEWS, The Semiconductor Equipment and Materials Weekly Briefing, Mar. 17, 2003, V10n22, 11 pgs.
Haddad Sameer
He Yi
Lingunis Emmanuil H.
Melik-Martirosian Ashot
Ramsbey Mark T.
Advanced Micro Devices , Inc.
Dang Phuc T.
Eschweiler & Associates LLC
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