PN junction floating gate EEPROM, flash EPROM device

Details PN junction floating gate EEPROM, flash EPROM device PN junction floating gate EEPROM, flash EPROM device

1996-06-17

1998-02-10

Fahmy, Wael

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257316, H01L 2976, H01L 29788

Patent

active

057172374

ABSTRACT:
Multi-state EEPROM and Flash EPROM devices with charge control are formed with a P-N junction floating gate with an N type capacitor on top of the channel area and a P type capacitor on top of the field oxide area. An additional mask and a P+/N+ implant instead of POCl.sub.3 doping are required to fabricate this device. The threshold voltage of this device well controlled by the ratio of C.sub.fp, capacitance of the P type capacitor and C.sub.fp capacitance of the N type capacitor. The coupling ratio "READ" and "WRITE" are exactly the same as current N type floating gate. The "ERASE" efficiency is improved by 1.5 volt higher voltage to the drain electrode of the EEPROM or the source electrode of a flash EPROM. Also, a good P-N junction floating gate, with reverse junction leakage less than 10 pA for 7 Volt reverse bias, is required to discharge the N type capacitor without affecting the P type capacitor.

REFERENCES:
patent: 4745079 (1988-05-01), Pfiester
patent: 5416738 (1995-05-01), Shrivastava
patent: 5469383 (1995-11-01), McElroy et al.

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