PMOS transistor with increased effective channel length in...

Details PMOS transistor with increased effective channel length in... PMOS transistor with increased effective channel length in...

2005-12-12

2008-12-23

Pham, Thanh V. (Department: 2894)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257S250000, C257S411000, C257SE29028, C438S296000

Reexamination Certificate

active

07468301

ABSTRACT:
In manufacturing a PMOS transistor, a semiconductor substrate having an active region and a field region is formed with a hard mask layer, which covers a center portion of the active region on the substrate in a lengthwise direction of a channel. The hard mask layer exposes the center portion of the active region in a widthwise direction of the channel and covers both edges of the substrate and the field region adjacent to the both edges. The substrate is etched to a predetermined depth using the hard mask layer as an etching barrier. The hard mask layer is then removed. A gate covering the center portion of the active region is formed on the lengthwise direction of the channel. Source and drain regions are formed at both edges of the gate.

REFERENCES:
patent: 6828188 (2004-12-01), Hirota et al.
patent: 2004/0108559 (2004-06-01), Sugii et al.
patent: 2004/0245563 (2004-12-01), Forbes
patent: 7-302902 (1995-11-01), None
patent: 2002-313950 (2002-10-01), None

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