Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2011-04-19
2011-04-19
Zarneke, David A (Department: 2891)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C257SE23127
Reexamination Certificate
active
07927998
ABSTRACT:
The plating method comprises the step of forming a resin layer10over a substrate16; the step of cutting the surface part of the resin layer10with a cutting tool12; the step of forming a seed layer36on the resin layer10by electroless plating; and the step of forming a plating film44on the seed layer36by electroplating. Suitable roughness can be give to the surface of the resin layer10, whereby the adhesion between the seed layer36and the resin layer10can be sufficiently ensured. Excessively deep pores are not formed in the surface of the resin layer10, as are by desmearing treatment, whereby a micronized pattern of a photoresist film40can be formed on the resin layer10. Thus, interconnections44, etc. can be formed over the resin layer10at a narrow pitch with high reliability ensured.
REFERENCES:
patent: 6428393 (2002-08-01), Yukawa et al.
patent: 2006/0027936 (2006-02-01), Mizukoshi et al.
patent: 5-37120 (1993-02-01), None
patent: 7-326614 (1995-12-01), None
patent: 9-82616 (1997-03-01), None
patent: 10-56251 (1998-02-01), None
patent: 11-6073 (1999-01-01), None
patent: 11-220262 (1999-08-01), None
patent: 2000-173954 (2000-06-01), None
patent: 2002-368428 (2000-12-01), None
patent: 2001-237542 (2001-08-01), None
patent: 2002-9416 (2002-01-01), None
patent: 3375555 (2002-11-01), None
patent: 2003-027250 (2003-01-01), None
patent: 2004-14611 (2004-01-01), None
patent: 2004-172530 (2004-06-01), None
Japanese Office Action dated Jun. 27, 2010, issued in corresponding Japanese Patent Application No. 2005-235229.
Baniecki John David
Kurihara Kazuaki
Mizukoshi Masataka
Nakagawa Kanae
Shioga Takeshi
Fujitsu Limited
Wagner Jenny L
Westerman Hattori Daniels & Adrian LLP
Zarneke David A
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