Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2000-06-20
2001-02-06
Powell, William (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C156S345420, C438S729000, C438S735000
Reexamination Certificate
active
06184146
ABSTRACT:
TECHNICAL FIELD
The invention pertains to plasma processing tools, dual-source plasma etchers, dual-source plasma etching methods, and methods of forming planar coil dual-source plasma etchers.
BACKGROUND OF THE INVENTION
Semiconductor processing typically involves depositing one or more layers of material and subsequently etching such layers to form a substrate feature. It is highly desirable to form uniform features over the entire surface of a semiconductor wafer. Yet, non-uniformities can arise based on the location of the feature relative to the wafer. For example, one type of semiconductor feature is a contact opening. Contact openings are typically etched through a dielectric material such as borophosphosilicate glass (BPSG). It has been observed that contact openings formed at or near the center of a wafer can have a different profile from contact openings formed away from the center of a wafer, e.g. at or near the wafer's periphery. Such non-uniformities are undesirable as they impart a degree of unpredictability in the finished integrated circuit.
This invention arose out of concerns associated with improving the uniformity with which substrate features, and in particular contact openings, are formed over a wafer. In particular, this invention arose out of concerns associated with improving dual-source plasma etchers and methods of using the same.
SUMMARY OF THE INVENTION
Plasma processing tools, dual-source plasma etchers, and etching methods are described. In one embodiment, a processing chamber is provided having an interior base and an interior sidewall joined with the base. A generally planar inductive source is mounted proximate the chamber. A dielectric liner is disposed within the chamber over the interior sidewall with the liner being received over less than an entirety of the interior sidewall. In a preferred embodiment, the interior sidewall has a groundable portion and the dielectric liner has a passageway positioned to expose the groundable interior sidewall portion. Subsequently, a plasma developed within the chamber is disposed along a grounding path which extends to the exposed interior sidewall. In another preferred embodiment, the dielectric liner is removably mounted within the processing chamber.
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Blalock Guy T.
Donohoe Kevin G.
Micro)n Technology, Inc.
Powell William
Wells, St. John, Roberts, Gregory & Matking P.S.
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