Plasma nitridation for reduced leakage gate dielectric layers

Semiconductor device manufacturing: process – Radiation or energy treatment modifying properties of...

Reexamination Certificate

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C438S775000, C257S649000

Reexamination Certificate

active

06667251

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor structures and manufacturing. More particularly, the invention relates to extremely thin dielectric layers and the formation thereof.
2. Background
Advances in semiconductor manufacturing technology have led to the integration of millions of circuit elements, such as transistors, on a single integrated circuit (IC). In order to integrate increasing numbers of circuit elements onto an integrated circuit it has been necessary to reduce the line widths of the various parts that make up an integrated circuit. Not only have interconnect line widths become smaller, but so have the dimensions of metal-oxide-semiconductor field effect transistors (MOSFETs).
MOSFETs are also sometimes referred to as insulated gate field effect transistors (IGFETs). Most commonly, these devices are referred to simply as FETs, and are so referred to herein.
Transistor scaling typically involves more than just the linear reduction of the FET width and length. For example, both source/drain (S/D) junction depth and gate dielectric thickness are also typically reduced in order to produce a FET with the desired electrical characteristics.
Over the years, a substantial amount of research and development in the field semiconductor manufacturing has been dedicated to providing reduced thickness dielectric layers, as mentioned above. However, to be suitable for use as a FET gate dielectric layer, these reduced thickness dielectric layers are typically required to have certain characteristics. Among the characteristics that are desirable for a FET gate dielectric are a dielectric constant that is greater than that of silicon dioxide, and an ability to reduce dopant outdiffusion from an overlying doped polysilicon gate electrode into or through the gate dielectric layer.
What is needed is a thin dielectric layer suitable for use as the gate dielectric layer in a FET, and what is further needed are repeatable methods of making such thin gate dielectric layers.


REFERENCES:
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patent: 6281138 (2001-08-01), Brady et al.
patent: 2002/0197884 (2002-12-01), Niimi
S.V. Hattangady, et al. “Ultrathin Nitrogen-Profile Engineered Gate Dielectric Films”, IEDM/IEEE 1996, pp. 495-498.
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Dixit Kapila et al. “Modeling and Optimization of Oxynitride Gate Dielectrics Formation by Remote Plasma Nitridation of Silicon Dioxide”, Journal of the Electrochemical-Society, 1999, The Electrochemical Society, Inc, pp. 111-1116, vol. 146.
R. Kraft et al. “Surface Nitridation of Silicon Dioxide with a High Density Nitrogen Plasma”, J. Vac. Sci. Technol. B(15)4 Jul./Aug. 1997, pp. 967-970, American Vacuum Society.
H. Niimi et al. “Controlled Incorporation of Nitrogen at the Top Surface of Silicon Oxide Gate Dielectrics”, , MRS Fall 1996, pp. 1-6.
Y. Wu et al., “Ultrathin Nitride/Oxide (N/O) Gate Dielectrics for p+ -Polysilicon Gated MOSFET's Prepared by a Combined Remote Plasma Enhanced CVD/Thermal Oxidation Process”, IEEE Electron Device Letters, Oct. 1998, pp. 367-369, vol. 19, No. 10.

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