Plasma etching process for MOS circuit pregate etching utiliizin

Details Plasma etching process for MOS circuit pregate etching utiliizin Plasma etching process for MOS circuit pregate etching utiliizin

1988-01-25

1989-02-28

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

134 2, 134 3, 134 28, 134 29, 134 30, 156646, 156651, 156653, 156657, 1566591, 156662, 20419237, 252 791, 252 792, 252 795, 437233, 437238, 437241, 437228, H01L 21306, B44C 122, C03C 1500, C03C 2506

Patent

active

048082597

ABSTRACT:
A method for etching of metal-oxide-semiconductor (MOS) devices utilizing a multi-step power reduction plasma etching recipe to reduce ion bombardment damage on the resulting surface. The multi-step power reduction recipe allows for reasonable throughput of wafers due to a relatively high etch rate at the upper layers of the surface followed by progressively lower power corresponding lower etch rates at the lower levels of the surface. The etching process is followed by a cleaning process to remove metallic contamination resulting from the plasma etching process to yield an excellent surface for growing low defect density MOS gate oxides with high dielectric integrity.

REFERENCES:
patent: 4461672 (1984-07-01), Musser
patent: 4528066 (1985-07-01), Merkling et al.
patent: 4662059 (1987-05-01), Smeltzer et al.
patent: 4690728 (1987-09-01), Tsang et al.
patent: 4720323 (1988-01-01), Sato
patent: 4729815 (1988-03-01), Leung

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