Plasma etching of dielectric layer with etch profile control

Details Plasma etching of dielectric layer with etch profile control Plasma etching of dielectric layer with etch profile control

2001-06-19

2004-06-08

Norton, Nadine G. (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S714000, C438S723000, C216S017000, C216S067000

Reexamination Certificate

active

06746961

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to an improved method for plasma etching a dielectric layer in the fabrication of integrated circuits.
BACKGROUND OF THE INVENTION
A common requirement in integrated circuit fabrication is plasma etching of openings such as contacts, vias and trenches in dielectric materials. The dielectric materials include doped silicon oxide such as fluorinated silicon oxide (FSG), undoped silicon oxide such as silicon dioxide, silicate glasses such as boron phosphate silicate glass (BPSG) and phosphate silicate glass (PSG), doped or undoped thermally grown silicon oxide, doped or undoped TEOS deposited silicon oxide, organic and inorganic low-k materials, etc. The dielectric dopants include boron, phosphorus and/or arsenic. The dielectric can overlie a conductive or semiconductive layer such as polycrystalline silicon, metals such as aluminum, copper, titanium, tungsten, molybdenum or alloys thereof, nitrides such as titanium nitride, metal silicides such as titanium silicide, cobalt silicide, tungsten silicide, molybdenum silicide, etc.
Various plasma etching techniques for etching openings in silicon oxide are disclosed in U.S. Pat. Nos. 4,615,764; 5,013,398; 5,013,400; 5,021,121; 5,022,958; 5,269,879; 5,529,657;5,595,627; 5,611,888 and 6,159,862. The plasma etching can be carried out in medium density reactors such as the parallel plate plasma reactor chambers described in the '398 patent or the triode type reactors described in the '400 patent or in high density reactors such as the inductive coupled reactors described in the '657 patent. Etching gas chemistries include SF
6
, NH
3
and an oxidizing component selected from CO
2
, O
2
, NO, SO
2
and H
2
O described in the '764 patent, the oxygen-free, Ar, CHF
3
and optional CF
4
gas mixture described in the '121 and '958 patents, the oxygen-free, fluorine-containing and nitrogen gas mixture described in the '879 patent, the CF
4
and CO gas mixture described in the '627 patent, the oxygen and CF
4
gas mixture described in the '400 patent, the oxygen, CF
4
and CH
4
gas mixture described in the '657 patent, and the Freon and neon gas mixture described in the '888 patent. The '862 patent describes a breakthrough procedure using Ar and O
2
or CHF
3
and SO
2
followed by etching SiO
2
using C
5
F
8
, O
2
, a carrier gas and optionally CO.
Techniques to achieve profile control of deep openings having high aspect ratios of at least 5:1 are disclosed in commonly owned U.S. Pat. Nos. 6,117,786 and 6,191,043B1. Of these, the '786 patent describes etching of openings in silicon oxide layers using a gas mixture containing fluorocarbon, oxygen and nitrogen reactants wherein the oxygen and nitrogen are added in amounts effective to control the profile of the etched opening. The '043 patent describes etching of deep openings 10 to 15 &mgr;m deep in a silicon layer by using a chlorine-containing etch gas chemistry to etch through a native oxide layer over the silicon layer and using a gas mixture containing an oxygen reactant gas, helium, an inert bombardment-enhancing gas and a fluorine-containing gas such as SF
6
, C
4
F
8
, CF
4
, NF
3
and CHF
3
to etch ultra deep openings in the silicon layer.
As device geometries become smaller and smaller, it is becoming necessary to plasma etch deep and narrow openings in silicon oxide. Accordingly, there is a need in the art for a plasma etching technique which achieves such deep and narrow openings. Further, it would be highly desirable to achieve such opening geometries without bowing of the sidewalls of the openings.
SUMMARY OF THE INVENTION
The invention provides a process of etching openings in a dielectric layer with profile control, comprising the steps of supporting a semiconductor substrate having a dielectric layer thereon in a plasma etch reactor, supplying an etchant gas to the plasma etch reactor, energizing the etchant gas into a plasma state and etching openings in the dielectric layer, the etchant gas comprising C
x
F
y
H
z
wherein x≧1, y≧1 and z≧0, a sulfur-containing gas and an oxygen-containing gas, the sulfur-containing gas and the oxygen-containing gas being added in amounts effective for profile control of the etched openings.
The etched openings can comprise vias, contacts and/or trenches of a dual damascene, a self-aligned contact or self-aligned trench structure. During etching of such openings, the C
x
F
y
H
z
forms a protective sidewall polymer on the sidewalls of the etched openings, the sulfur-containing gas protects the sidewall polymer from excessive attack by the oxygen-containing gas and the oxygen-containing gas maintains a desired thickness of the sidewall polymer. In the case where the sulfur-containing gas is SO
2
, undissociated SO
2
molecules react with polymer at the bottoms of the etched openings to prevent etch stop under bombardment of directional ions.
The plasma etch reactor can comprise an ECR plasma reactor, an inductively coupled plasma reactor, a capacitively coupled plasma reactor, a helicon plasma reactor or a magnetron plasma reactor. For instance, the plasma etch reactor can comprise a dual frequency capacitively coupled plasma reactor including an upper showerhead electrode and a bottom electrode, RF energy being supplied at two different frequencies to either the bottom electrode or at different first and second frequencies to the showerhead electrode and bottom electrode. In the case where the plasma etch reactor is a capacitively coupled plasma reactor, the reactor can have a powered showerhead electrode and a powered bottom electrode, the showerhead electrode being supplied 500 to 3000 watts of RF energy and the bottom electrode being supplied 500 to 3000 watts of RF energy.
According to a preferred embodiment, the sulfur-containing gas is SO
2
and the oxygen-containing gas is O
2
, the SO
2
and O
2
being added in amounts effective to provide undissociated SO
2
molecules which react with polymer at bottoms of the etched openings to prevent etch stop under bombardment of directional ions. The ratio of flow rates of the sulfur-containing gas to the oxygen-containing gas can be 0.5:1 to 1.5:1. During the process, pressure in the plasma etch reactor can be 5 to 200 mTorr and/or temperature of the substrate support can be −20° C. to +80° C. The etchant gas can include a carrier gas selected from the group consisting of He, Ne, Kr, Xe and Ar, the carrier gas being supplied to the plasma etch reactor at a flow rate of 5 to 1000 sccm.
The C
x
F
y
H
z
gas can be a mixture of hydrogen-containing and hydrogen-free fluorocarbon gases supplied to the plasma etch reactor at a total flow rate of 5 to 100 sccm. The sulfur-containing gas preferably consists of SO
2
and the oxygen-containing gas preferably consists of O
2
, each of the SO
2
and O
2
gases being supplied to the plasma etch reactor at a flow rate of 1 to 30 sccm. In the case where the dielectric layer is BPSG, the etchant gas can include SO
2
and O
2
supplied to the plasma etch reactor with flow rates providing a SO
2
:O
2
flow rate ratio of 1:2 to 2:1.
In the process of the invention it is possible to obtain etched openings 0.30 &mgr;m or smaller having substantially straight profiles wherein top, middle and bottom critical dimensions of the openings are substantially the same, and the openings have an aspect ratio of at least 5:1. The dielectric layer can consist of a single material or a stack of layers such as low-k materials with or without etch stop layers therebetween. The openings can be etched to depths of at least 2 &mgr;m or at least 3 &mgr;m and an RF bias can be applied to the semiconductor substrate during the etching step. For example, the etched openings can be 0.25 &mgr;m or smaller sized openings having substantially straight profiles wherein top, middle and bottom critical dimensions of the openings are substantially the same, and the openings have an aspect ratio of at least 10:1.
A preferred etchant gas includes C
4
F
8
,

Affiliated with

Also associated with

Rating

Plasma etching of dielectric layer with etch profile control does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Plasma etching of dielectric layer with etch profile control, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Plasma etching of dielectric layer with etch profile control will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3338243