Semiconductor device manufacturing: process – Including control responsive to sensed condition – Optical characteristic sensed
Reexamination Certificate
2002-05-17
2004-11-30
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Including control responsive to sensed condition
Optical characteristic sensed
Reexamination Certificate
active
06825051
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates in general to a plasma etch resistant coating on susceptors, and more specifically to a protective coating for susceptors used in semiconductor deposition chambers, and methods of using the same.
BACKGROUND OF THE INVENTION
In the generation of semiconductor devices, such as devices designed for memories and microprocessors, various thin films are deposited onto a semiconductor substrate. These thin films include dielectric films. Examples include silicon nitride (SiN), which is used among other things as an oxidation-resistant masking film, and silicon dioxide (SiO), which is used among other things as a passivation film.
High-temperature ovens, called reactors, are used to generate semiconductor substrates. For such a process, one or more substrates, such as silicon wafers, are placed on a wafer support inside the reaction chamber. Both the wafer and support are heated to a desired temperature. Wafer supports that aid in absorbing radiant heat are known as susceptors. In a typical wafer treatment step, reactant gases are passed over the heated wafer, causing the chemical vapor deposition (CVD) of a thin layer on the wafer. Various process conditions, particularly temperature uniformity and reactant gas distribution, must be carefully controlled to ensure a high quality of the resulting layers.
Susceptors are typically formed of silicon carbide (SiC)-coated graphite components that can be additionally coated to stabilize emissivity. For example, in order to have uniform thermal behavior during substrate processing, components in a SiN deposition tool can be additionally coated, prior to processing of the substrates, with silicon nitride. The initial SiN coating on the susceptor causes the susceptor emissivity, which affects temperature control, to be roughly the same at the beginning and end of a run, despite continued SiN build-up on the susceptor as SiN is deposited on a plurality of wafers in series.
Thus, in a typical process run for a SiN CVD reactor, a susceptor is introduced into the chamber, the susceptor is coated with silicon nitride in the chamber, and then wafers are introduced sequentially for deposition of silicon nitride on the wafers. Between wafers, or after several wafers are processed, a plasma clean step is conducted to remove deposits that are left on the walls of the chamber and also on the susceptor.
During the cleaning and removal of SiN deposits, the underlying SiC tends to get damaged. Accordingly, a need exists for an improved coating for protection of semiconductor components.
SUMMARY OF THE INVENTION
In accordance with one aspect of the present invention, a susceptor comprising a silicon oxynitride coating is provided for a semiconductor reactor configured for plasma etch processing.
In accordance with another aspect of the present invention, a method of preparing a wafer holder for deposition is provided. The method includes introducing the wafer holder into the chamber, coating the wafer holder with a primary coating of silicon nitride in the chamber, and oxidizing the primary silicon nitride coating on the wafer holder prior to processing of wafers.
In the illustrated embodiments, the susceptor is a SiC-coated graphite susceptor, and the reactor is configured for silicon nitride deposition. The primary coating of silicon nitride is formed by thermal CVD and preferably has a thickness between about 500 Å and 2.0 &mgr;m. Oxidizing of the primary silicon nitride coating comprises flowing an oxygen source selected from the group consisting of oxygen, nitric oxide, and nitrous oxide. Oxidizing preferably forms between about 5 Å and 200 Å of silicon oxynitride.
In one preferred embodiment, oxidizing comprises non-uniformly oxidizing the primary silicon nitride coating. Non-uniformly oxidizing can comprise employing an inert gas to direct an oxygen source non-uniformly over the wafer holder and/or adjusting temperature offsets. After one or more cycles of silicon nitride deposition, the reactor is configured for plasma cleaning of reactor surfaces.
In another aspect, a process is provided for using an oxidized silicon nitride coating to protect a susceptor from plasma cleaning of excess silicon nitride after at least one cycle of wafer processing.
In another aspect, a method of processing semiconductor substrates comprising preparing a susceptor by providing a primary coating on the susceptor and oxidizing the primary coating prior to processing of substrates. A substrate is loaded onto susceptor, followed by depositing silicon nitride onto the substrate. The silicon nitride coated substrate is removed from the susceptor. The susceptor is then subjected to plasma cleaning for removal of silicon nitride from the depositing. In a preferred embodiment, the primary coating comprises silicon nitride and multiple substrates are coated with silicon nitride in sequence before plasma cleaning. The coating serves to protect the susceptor used in semiconductor reactors from the plasma cleaning process.
In the illustrated embodiments, the oxidized silicon nitride layer that overlies the silicon carbide coating on the chamber components provides superior etch selectivity, as compared to etching SiN over SiC. This has been found particularly advantageous where the coatings are preferentially attacked in various areas due to non-uniform distribution of cleaning radicals in the reactor chamber.
REFERENCES:
patent: 3011006 (1961-11-01), Nicholson et al.
patent: 3874919 (1975-04-01), Lehman
patent: 4374158 (1983-02-01), Taniguchi et al.
patent: 4377347 (1983-03-01), Hanmyo et al.
patent: 4389967 (1983-06-01), Shimoda et al.
patent: 4428975 (1984-01-01), Dahm et al.
patent: 4499354 (1985-02-01), Hill et al.
patent: 4522849 (1985-06-01), Lewandowski
patent: 4592307 (1986-06-01), Jolly
patent: 4633051 (1986-12-01), Olson
patent: 4653428 (1987-03-01), Wilson et al.
patent: 4692556 (1987-09-01), Bollen et al.
patent: 4976996 (1990-12-01), Monkowski et al.
patent: 4978567 (1990-12-01), Miller
patent: 4984904 (1991-01-01), Nakano et al.
patent: 5027746 (1991-07-01), Frijlink
patent: 5065698 (1991-11-01), Koike
patent: 5104514 (1992-04-01), Quartarone
patent: 5129958 (1992-07-01), Nagashima et al.
patent: 5246500 (1993-09-01), Samata et al.
patent: 5271967 (1993-12-01), Kramer et al.
patent: 5315092 (1994-05-01), Takahashi et al.
patent: 5336327 (1994-08-01), Lee
patent: 5360269 (1994-11-01), Ogawa et al.
patent: 5421893 (1995-06-01), Perlov
patent: 5456761 (1995-10-01), Auger et al.
patent: 5474618 (1995-12-01), Allaire
patent: 5493987 (1996-02-01), McDiarmid et al.
patent: 5514439 (1996-05-01), Sibley
patent: 5562774 (1996-10-01), Breidenbach et al.
patent: 5571333 (1996-11-01), Kanaya
patent: 5594482 (1997-01-01), Ohashi
patent: 5728629 (1998-03-01), Mizuno et al.
patent: 5788799 (1998-08-01), Steger et al.
patent: 5798016 (1998-08-01), Oehrlein et al.
patent: 5874368 (1999-02-01), Laxman et al.
patent: 5902407 (1999-05-01), De Boer et al.
patent: 5904778 (1999-05-01), Lu et al.
patent: 5910221 (1999-06-01), Wu
patent: 6056823 (2000-05-01), Sajoto et al.
patent: 6066209 (2000-05-01), Sajoto et al.
patent: 6071573 (2000-06-01), Koemtzopoulos et al.
patent: 6120640 (2000-09-01), Shih et al.
patent: 6129808 (2000-10-01), Wicker et al.
patent: 6170429 (2001-01-01), Schoepp et al.
patent: 6214425 (2001-04-01), Spinelli et al.
patent: 6227140 (2001-05-01), Kennedy et al.
patent: 6325857 (2001-12-01), Miyoshi
patent: 6325858 (2001-12-01), Wengert et al.
patent: 6342691 (2002-01-01), Johnsgard et al.
patent: 2001/0001954 (2001-05-01), Urabe
patent: 2002/0096115 (2002-07-01), Urabe
patent: 2003/0035905 (2003-02-01), Lieberman et al.
patent: 0 229 488 (1987-07-01), None
patent: WO 95/31582 (1995-11-01), None
patent: WO 97/06288 (1997-02-01), None
patent: WO 99/23276 (1999-05-01), None
Moslehi et al., “Compositional Studies of Thermally Nitrided Silicon Dioxide (Nitroxide)”,J. Electrochem. Soc., vol. 132, No. 9, pp. 2189-2197 (Sep. 1985).
Murarka et al., “Thermal Nitridation of Silicon in Ammonia Gas: Compositio
AmRhein Fred
Pomarede Christophe
ASM America Inc.
Knobbe Martens Olson & Bear LLP
Le Thao P.
Nelms David
LandOfFree
Plasma etch resistant coating and process does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Plasma etch resistant coating and process, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Plasma etch resistant coating and process will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3298556