Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-08-04
2001-07-03
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S592000, C438S664000
Reexamination Certificate
active
06255179
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention is directed to the manufacture of semiconductor components and, in particular, to the formation of field effect transistors having decreased resistance.
2. Description of Related Art
Typically, in forming a field effect transistor (FET), a silicon substrate is provided having diffusion areas and isolation trenches formed thereon. The substrate may be a silicon on insulator (SOI) substrate with shallow trench isolations. Diffusion areas such as N-wells and P-wells are formed by implantation and annealing methods well known in the art.
An oxide may be grown and polysilicon deposited on the surface of the substrate, patterned with a photoresist, and etched to form desired gate structures. Once the polysilicon gate structures are in place, spacers are formed adjacent to the gates to tailor the FET appropriately and prevent shorting of the gate to the diffusion areas. A conformal dielectric layer of silicon nitride or silicon oxide is deposited over the substrate and gate structures. The conformal dielectric layer is then isotropically etched to leave side wall spacers on either side of each gate structure.
To form the source and drain regions on the FET, dopants such as boron, and phosphorus are implanted into the wafer. A photoresist is applied to the substrate and patterned. The pattern leaves exposed areas on the substrate where a first dopant, for example a P+ dopant, is implanted to form a P+ source region and P+ drain region as well as dope the polysilicon gate structures. Thereafter, the photoresist is stripped and a reverse photoresist is applied which has a pattern corresponding to a N+ dopant. The second dopant is then imbedded into the wafer. Once the source and drain regions are formed, the wafer is annealed to activate the source and drain regions.
Typically, once the source and drain regions are formed, a metal is deposited on the surface of the wafer to form the metal silicide which reduces the resistance of the polysilicon lines. However, contaminants from the previous processing may cause discontinuities in the metal silicide formation by preventing the metal from fully reacting with the polysilicon. The discontinuities increase the resistance of the polysilicon lines and the source and drain regions.
Prior to silicide formation, the wafer is typically cleaned by a series of wet and dry cleans to remove contaminants. These cleans are intended to remove contaminants such as resist residuals, implant residuals, metals, and particles from the surface of the silicon wafer. However, these cleans while removing some or all of the native oxide do not remove more than a few mono-layers of silicon from the substrate and are insufficient to substantially remove all contaminants.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a method of removing contaminants from a surface and a top layer of a silicon wafer prior to silicide formation to reduce discontinuities in the metal silicide.
It is another object of the present invention to provide a method of forming a metal silicide having lower resistance on a silicon wafer.
A further object of the present invention is to provide a method of forming a field effect transistor having reduced resistance in the polysilicon lines and the source and drain regions.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.
SUMMARY OF THE INVENTION
The above and other objects and advantages, which will be apparent to one of skill in the art, are achieved in the present invention which is directed to, in a first aspect, a method of preparing a silicon wafer for silicide formation comprising the steps of: (a) providing a silicon wafer having formed thereon doped source and drain regions, the source and drain regions having polysilicon gates; (b) activating the source and drain regions; (c) providing a plasma source; and (d) treating the surface of the wafer with the plasma source, wherein subsequent silicide formation on the wafer has substantially reduced discontinuities and lowered resistance.
The present invention is directed to, in another aspect, a method of forming a silicide layer having reduced discontinuities and lowered resistance on a silicon wafer comprising the steps of: (a) providing a silicon wafer having activated source and drain regions formed thereon, the source and drain regions having polysilicon gate structures; (b) placing the silicon wafer in a chamber and providing a plasma source; (c) reacting a sufficient depth of a surface of the silicon wafer with the plasma source; (d) etching the surface of the wafer with hydrofluoric acid; and (e) depositing a metal on the surface of the silicon wafer.
The present invention is directed to, in yet another aspect, a method of forming a field effect transistor having lowered resistance comprising the steps of: (a) providing a silicon wafer having diffusion areas and isolation areas with polysilicon gate structures having side wall spacers thereon; (b) forming source and drain regions by doping the wafer at desired sites and activating the source and drain regions; (c) reacting a sufficient depth of the wafer having activated source and drain regions with a plasma source such that contaminants on the surface of the wafer are treated with the plasma source; (d) etching the surface of the wafer with hydrofluoric acid to further remove contaminants on the surface of the wafer; and (e) depositing a metal on the surface of the wafer and forming a metal silicide thereon.
In practicing the present invention, the plasma source most preferably treats the surface of the wafer in a controllable manner and to a sufficient depth such that device parametrics on the wafer remain intact.
The plasma source may, preferably, comprise an ozone plasma at about 350 to about 450 Watts, at a pressure of about 6 to about 10 mTorr, at a temperature of about 350 to about 450° C. with an ozone flow rate of about 3700 to about 4100 sccm to substantially oxidize about 10 to about 200 Å of a surface of the wafer.
The plasma source may, preferably, comprise an NF
3
/Ar plasma source at about 40 to about 80 Watts, at a pressure of about 10 to about 35 mTorr, at a temperature of about 17 to about 45° C. with an Ar flow rate of about 75 to about 125 sccm and an NF
3
flow rate of about 3.75 to about 6.25 sccm to etch about 10 to about 200 Å of a surface of the wafer.
The plasma source may also, preferably, comprise a plasma containing a fluorocarbon at about 75 to about 125 Watts, at a pressure of about 20 to about 60 mTorr, at a temperature of about 10 to about 45° C. with an O
2
flow rate of about 30 to about 90 sccm and a CHF
3
flow rate of about 30 to about 90 sccm to etch about 10 to about 200 Å of a surface of the wafer.
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Cantell Marc W.
Giewont Kenneth
Lasky Jerome B.
Peterson Kirk D.
DeLio & Peterson
International Business Machines - Corporation
Lindsay Jr. Walter L.
Niebling John F.
Sabo William D.
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