Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1998-12-28
2004-02-03
Kunemund, Robert (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S723000, C438S724000, C438S725000
Reexamination Certificate
active
06686292
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to methods for forming composite multilayer stack layers on substrates within microelectronics fabrications. More particularly, the present invention relates to plasma etch methods for forming patterned composite multi-layer stack layers within microelectronics fabrications.
2. Description of the Related Art
Microelectronics fabrications are formed from microelectronics substrates over which are formed patterned microelectronics conductor layers which are separated by microelectronics dielectric layers.
As microelectronics fabrication integration levels have increased and microelectronics fabrication device and patterned conductor layer dimensions have decreased, it has become increasingly important to efficiently form within microelectronics fabrications patterned composite silicon containing dielectric layer/polysilicon layer/multi-layer stack layers. Such patterned silicon containing dielectric layer/polysilicon layer/multi-layer stack layers may be employed within microelectronics fabrications for forming various microelectronics structures. In particular, such patterned composite silicon containing dielectric layer/polysilicon layer/multi-layer stack layers may be formed on underlying layers of silicon oxide gate oxide dielectric layers which in turn are formed upon or over silicon semiconductor substrates employed in microelectronics fabrications for applications such as but not limited to polysilicon capacitors, as well as gate electrodes employed within field effect transistors (FETs) such as electrically erasable programmable read only memory (EEPROM) field effect transistors (FETs) which are also known as electrically alterable programmable read only memory (EAPROM) field effect transistors (FETs).
While patterned composite silicon containing dielectric layer/polysilicon layer multi-layer stack layers are thus desirable within the art of microelectronics fabrication, patterned composite silicon containing dielectric layer/polysilicon layer multi-layer stack layers are nonetheless not formed entirely without problems within microelectronics fabrication. In particular, patterned composite silicon containing dielectric layer/polysilicon layer multi-layer stack layers when formed within microelectronics fabrications while employing a conventional plasma etch method employing a patterned photoresist etch mask layer often suffer from detrimental effects, such as non-uniform dimensions of patterns, in particular conductor linewidths, and polymeric residues from etching the desired pattern in the dielectric layer/polysilicon layer multi-layer stack. Although polymeric residue formation and other defect effects may often be attenuated when forming patterned composite silicon containing dielectric layer/polysilicon layer multi-layer stack layers while employing more sophisticated plasma etch methods, such alternative plasma etch methods typically provide enhanced process complexity and cost when forming patterned composite silicon containing dielectric layer/polysilicon layer multi-layer stack layers.
It is thus towards the goal of forming with enhanced linewidth uniformity and attenuated polymeric residue formation within a microelectronics fabrication a patterned composite silicon containing dielectric layer/polysilicon layer/multi-layer stack layer that the present invention is more specifically directed. In a more general sense, the present invention is also directed towards the goal of forming with enhanced linewidth uniformity, attenuated polymeric residue formation and reduced defect levels within a microelectronics fabrication a patterned composite silicon containing dielectric layer/silicon layer/multi-layer stack layer, where the silicon layer need not necessarily be a polysilicon layer.
Various plasma etch methods have been disclosed within the art of microelectronics fabrication for forming patterned microelectronics layers within microelectronics fabrications.
For example, Lii, in “ULSI Technology” Chang and Sze, eds., McGraw-Hill Company, Inc.(1997), p.354, discloses the chemistries and process parameters suitable for forming patterned layers by plasma etching methods. Such patterned layers may be formed from dielectric materials such as silicon oxide and silicon nitride, as well as conductive materials such as polysilicon, tungsten suicide, aluminum and the like.
Further, Becker et al., in U.S. Pat. No. 5,094,712, discloses a plasma etch method for efficiently forming an anisotropically patterned composite silicon oxide/tungsten silicide/polysilicon stack layer within an integrated circuit microelectronics fabrication. The method employs a single plasma reactor chamber within which there is sequentially and anisotropically etched: (1) a blanket silicon oxide layer while employing a carbon tetrafluoride, trifluoromethane and inert gas plasma to form a patterned silicon oxide layer; (2) a blanket tungsten silicide layer while employing a helium, oxygen and sulfur hexafluoride plasma to form a patterned tungsten silicide layer co-extensive with the patterned silicon oxide layer; and (3) a blanket polysilicon layer while employing a hydrogen bromide and chlorine plasma to form a patterned polysilicon layer co-extensive with the patterned tungsten silicide layer and the patterned silicon oxide layer.
Still further, Becker, in U.S. Pat. No. 5,691,246, discloses a method for plasma etching, in a single chamber, a silicon oxide/polysilicon/silicon oxide multilayer structure. Within the method, both silicon oxide layers are anisotropically etched and the polysilicon layer is isotropically etched to recess the edges of the polysilicon layer from the edges of the silicon oxide layers.
Yet further still, Long et al., in U.S. Pat. No. 5,013,392, disclose a method for etching anisotropically within a single reactor chamber a multi-layer structure comprising a silicon dioxide/polycrystalline silicon/silicon dioxide stack layer. The method employs a first etching gas atmosphere comprising a mixture of SF6, CHF3 and He for etching the first silicon dioxide layer, and a second etching gas atmosphere comprising a mixture of HBr and He for etching the polycrystalline silicon.
Finally, Langley., in U.S. Pat. No. 5,201,993, discloses a method for plasma etching anisotropically, in a single reactor chamber, a silicon oxide /silicide stack layer while employing an inert carrier gas incorporated into an etching atmosphere. The fully etched multi-layer structure has a vertical profile at or near 90 degrees from the horizontal, with no bowing or notching. The method employs a silicon oxide etch step which utilizes a gas mixture comprising C2F6, CF4, CHF3 and an inert carrier gas as the etching gas atmosphere.
Desirable in the art of microelectronics fabrication are methods through which there may be formed with uniform linewidth and with attenuated polymer residue formation and defect levels a patterned composite silicon containing dielectric layer/silicon layer/multi-layer stack layer within a microelectronics fabrication. More particularly desirable in the art of microelectronics fabrication are methods through which there may efficiently and with attenuated polymer residue formation and reduced particulate defect levels be formed a patterned composite single or multiple silicon containing dielectric layer/polysilicon layer/multi-layer stack upon a silicon oxide layer upon a semiconductor substrate employed within a microelectronics fabrication.
It is towards the foregoing goals that the present invention is both generally and more specifically directed.
SUMMARY OF THE INVENTION
A first object of the present invention is to provide a method for forming within a microelectronics fabrication a patterned composite silicon containing dielectric layer/polysilicon layer multi-layer stack layer.
A second object of the present invention is to provide a method in accord with the first object of the present invention, where the patterned composite silicon containing dielectric layer/polysilicon layer mu
Pan Sheng-Liang
Yang Szu-Hung
Ackerman Stephen B.
Kunemund Robert
Mackey Terrence M.
Saile George O.
Stanton Stephen G.
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