Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1998-09-04
2002-08-27
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S711000, C438S717000, C438S723000
Reexamination Certificate
active
06440863
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to plasma etch methods for forming patterned layers within microelectronics fabrications. More particularly, the present invention relates t
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plasma etch methods for forming patterned oxygen containing plasma etchable layers within microelectronics fabrications.
2. Description of the Related Art
Microelectronics fabrications are formed from microelectronics substrates over which are formed patterned microelectronics conductor layers which are separated by microelectronics dielectric layers.
As microelectronics integration levels have increased and microelectronics device and patterned conductor layer dimensions have decreased, it has become increasingly common within the art of microelectronics fabrication to employ interposed between the patterns of narrow linewidth dimension and/or narrow pitch dimension patterned microelectronics conductor interconnect layers within microelectronics fabrications microelectronics dielectric layers formed of low dielectric constant dielectric materials. Such patterned microelectronics conductor interconnect layers often access within the microelectronics fabrications within which they are formed patterned conductor contact stud layers or patterned conductor interconnect stud layers. For the purposes of the present disclosure, low dielectric constant dielectric materials are intended as dielectric materials having a dielectric constant of less than about 3.0. For comparison purposes, dielectric layers formed employing conventional silicon oxide dielectric materials, silicon nitride dielectric materials or silicon oxynitride dielectric materials typically have dielectric constants in the range of from about 4.0 to about 7.0.
Microelectronics dielectric layers formed of low dielectric constant dielectric materials are desirable interposed between the patterns of narrow linewidth dimension and/or narrow pitch dimension patterned microelectronics conductor layers within microelectronics fabrications since such dielectric layers formed from such low dielectric constant dielectric materials provide dielectric layers which assist in providing microelectronics fabrications exhibiting enhanced microelectronics fabrication speed, attenuated patterned microelectronics conductor layer parasitic capacitance, and attenuated patterned microelectronics conductor layer cross-talk.
Low dielectric constant dielectric materials which may be employed for forming low dielectric constant microelectronics dielectric layers within microelectronics fabrications are typically materials with hydrogen and/or carbon content, such as but not limited to organic polymer spin-on-polymer dielectric materials (such as but not limited to polyimide organic polymer spin-on-polymer dielectric materials, fluorinated polyimide organic polymer spin-on-polymer dielectric materials, poly-arylene-ether organic polymer spin-on-polymer dielectric materials and fluorinated poly-arylene-ether organic polymer spin-on-polymer dielectric materials and fluorinated poly-arylene-ether organic polymer spin-on-polymer dielectric materials), amorphous carbon dielectric materials (such as but not limited to amorphous carbon and fluorinated amorphous carbon), and silsesgiuoxane spin-on-glass (SOG) dielectric materials (such as but not limited to hydrogen silsesquioxane spin-on-glass (SOG) dielectric materials, carbon bonded hydrocarbon silsesquioxane spin-on-glass (SOG) dielectric materials, and carbon bonded fluorocarbon silsesquioxane spin-on-glass (SOG) dielectric materials).
While organic polymer spin-on-polymer dielectric materials, amorphous carbon dielectric materials, and silsesquioxane spin-on-glass (SOG) dielectric materials are thus desirable within the art of microelectronics fabrication for forming low dielectric constant microelectronics dielectric layers interposed between the patterns of patterned conductor interconnect layers which access patterned conductor stud layers within microelectronics fabrications, such microelectronics fabrication structures are often not formed entirely without difficulty. In particular, when such structures are formed employing a damascene method which employs a patterning of a blanket oxygen containing plasma etchable low dielectric constant dielectric layer (such as formed employing an organic polymer spin-on-polymer dielectric material or an amorphous carbon dielectric material) to form a patterned oxygen containing plasma etchable low dielectric constant dielectric layer while employing a hard mask layer and an oxygen containing plasma to form a trench and/or via defined by the patterned oxygen containing plasma etchable low dielectric constant dielectric layer prior to forming a patterned conductor interconnect layer and/or patterned conductor stud layer within the trench and/or via while employing the damascene method, it is often difficult to control the linewidth and sidewall profile of the patterned oxygen containing plasma etchable low dielectric constant dielectric layer, and thus also the linewidth and sidewall profile of the trench and/or via. Trenches and/or vias formed with inadequately controlled linewidth and non-uniform sidewall profile are undesirable within microelectronics fabrications since patterned conductor interconnect layers and/or patterned conductor stud layers formed within those microelectronics fabrications are then also formed with inadequate linewidth control and non-uniform sidewall profiles.
It is thus towards the goal of forming within a microelectronics fabrication a patterned oxygen containing plasma etchable dielectric layer (preferably an oxygen containing plasma etchable low dielectric constant dielectric layer) within which is formed a trench and/or via which may be filled with a patterned conductor interconnect layer and/or a patterned conductor stud layer employing a damascene method, with enhanced linewidth control and uniform sidewall profile, that the present invention is more specifically directed. In a more general sense, the present invention is also directed towards a method for forming a patterned oxygen containing plasma etchable layer, which need not necessarily be a patterned oxygen containing plasma etchable dielectric layer, with enhanced linewidth control and uniform sidewall profile.
Various methods have been disclosed in the art of microelectronics fabrication for forming patterned microelectronics layers within microelectronics fabrications.
For example, Y. J. T. Lii in
ULSI Technology
, C. Y. Chang and S. M. Sze, eds., Mc-Graw Hill (New York: 1996), pp. 346-55 discloses various plasma process reactor configurations and plasma etchant gas compositions which may be employed when forming patterned layers within microelectronics fabrications while employing plasma etch methods.
In addition, Shan et al., in U.S. Pat. No. 5,514,247, discloses a method for forming within a microelectronics fabrication a via through a dielectric layer to access a conductor metal layer formed beneath the dielectric layer, without forming a sputtered conductor metal residue layer upon a sidewall of the via. The method employs within an etchant gas composition which is employed to etch the via through the dielectric layer a gas which reacts with the conductor metal to form a volatile and readily evacuable material.
Further, Chang et al., in U.S. Pat. No. 5,559,055 discloses a method for forming within a microelectronics fabrication, interposed between a series of patterns of a patterned conductor layer, an interlayer dielectric layer with decreased dielectric constant. The method employs a subtractive etching of an otherwise conventional patterned dielectric layer interposed between the patterns of the patterned conductor layer to form within the microelectronics fabrication a series of air filled voids interposed between patterns of the patterned conductor layer, where the series of air filled voids may subsequently be at least partially filled with a low dielectric constant dielectric material.
Still further, Havemann, in U.S
Chen Chao-Cheng
Tao Hun-Jan
Tsai Chia-Shiun
Ackerman Stephen B.
Saile George O.
Taiwan Semiconductor Manufacturing Company
Tran Binh X.
Utech Benjamin L.
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