Plasma etch chemistry and method of improving etch control

Details Plasma etch chemistry and method of improving etch control Plasma etch chemistry and method of improving etch control

1999-06-15

2002-04-16

Quach, T. N. (Department: 2814)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S706000, C438S710000, C438S723000

Reexamination Certificate

active

06372634

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit manufacturing and, for example, to forming openings into or through a material that exists above a semiconductor substrate.
2. Description of the Related Art
In the fabrication of semiconductor devices, numerous conductive device regions and layers are formed in or on a semiconductor substrate. The conductive regions and layers of the device are isolated from one another by a dielectric, such as silicon dioxide (“oxide”). At several stages during fabrication, it is necessary to make openings in a material, such as a dielectric, to allow for contact to underlying regions or layers. Generally, an opening through a dielectric exposing a diffusion region within a semiconductor substrate or an opening through a dielectric layer between polycrystalline silicon (“polysilicon”) and the first metal layer is called a “contact opening”, while an opening in other dielectric layers, such as an opening through an interlevel dielectric layer (“ILD”), is referred to as a “via”. As used herein, an “opening” will be understood to refer to any type of opening through any type of material, such as a dielectric layer, regardless of the stage of processing, layer exposed, or function of the opening.
To form the openings in the dielectric layer, a patterning layer of photoresist is formed over the dielectric layer. Openings are formed in the photoresist corresponding to the regions of the dielectric layer where the dielectric layer openings are to be formed. The openings in the photoresist may be formed using, for example, photolithography patterning and etch techniques that are well known to those of ordinary skill in the art.
In most modem processes of forming openings in the dielectric layer, a dry etch is performed subsequent to patterning the photoresist, wherein the dielectric layer is exposed to a plasma, formed in a flow of one or more gases. Typically, one or more halocarbons and/or one or more other halogenated compounds are used as the etchant gas. For example, CF
4
, CHF
3
, C
2
F
6
, SF
6
, NF
3
, and other gases may be used as the etchant gas. Additionally, gases such as O
2
, Ar, N
2
, or He, for example, may be added to the gas flow. The particular gas mixture used will depend on, for example, the characteristics of the dielectric being etched, the stage of processing, the etch tool being used, and the desired etch characteristics, such as etch rate, wall slope, and anisotropy, among others.
Many of the etch characteristics are generally believed to be affected by a passivation material that may occur with the etch process. The passivation material may contain carbon, possibly derived from carbon within the etchant and/or from carbon-based compounds within or upon the material being etched. The carbon-containing residue may be a polymer. The carbon-containing residue may form concurrently with the dry etch. For this reason, the fluorine-to-carbon ratio (“F/C ratio”) in the plasma is considered an important determinant in the dry etch. For a more thorough discussion of dry etching, see S. Wolf and R. N. Tauber,
Silicon Processing for the VLSI ERA, Volume
1, pp. 539-585 (Lattice Press, Sunset Beach, Calif.; 1986), incorporate herein by reference.
As the dimensions of integrated circuits have been reduced, problems with uniformity of lateral dimensions of the openings have increased. As used herein, “lateral dimension” refers to the dimension of an opening fabricated in a dielectric layer, typically as measured in a direction substantially parallel to an upper surface of a semiconductor substrate upon which the integrated circuit is formed. “Critical dimension” as used in this application refers to the design value of the opening in the dielectric and, by extension, to the lateral size of an opening in the patterned photoresist above the dielectric layer site where the dielectric opening is to be formed. Critical dimensions are of interest since they can represent the smallest lateral dimension that can be formed on a topography using various techniques such as photolithography. A lateral dimension can be represented by an opening formed within a film, a structure formed upon a film or substrate, and/or a spacing between structures.
In general, lateral dimensions require close control to prevent deviation from the critical dimensions and to ensure optimal device performance. “Dimensional uniformity” as used in this application refers to the correspondence between the design value of a critical dimension and the value of the corresponding lateral dimension obtained during fabrication. For example, a combination of CF
4
and/or CHF
3
may be used as etchant gases for performing a plasma etch through a patterned photoresist, and Ar, and N
2
may be used as a carrier/inert gas in the plasma etch chamber. Such a combination typically provides good dimensional uniformity for openings formed through a dielectric (i.e., good correspondence between the design values and the values obtained during fabrication).
FIG. 1
depicts a portion of a semiconductor topography
90
including a conductive line
2
with a dielectric layer
4
formed over the conductive line. According to an embodiment, conductive line
2
may include a metal. According to an alternative embodiment, conductive line
2
may include doped polysilicon. Conductive line
2
may be spaced above a semiconductor substrate on a wafer (not shown) by intervening layers of dielectric, semiconductive and/or conductive material. Alternatively, dielectric layer
4
may be formed directly upon portions of the semiconductor substrate. Patterned photoresist
6
resides upon dielectric layer
4
.
Openings
10
,
20
, and
30
may be formed in photoresist layer
6
using well-known photolithography techniques. Openings
10
,
20
, and
30
are preferably formed with predetermined lateral dimensions C
1
, C
2
, and C
3
, respectively. Opening
20
is shown to be near the center
3
of the wafer, while openings
10
and
30
are shown near the edges
1
of the wafer. According to an embodiment, the lateral dimensions may be substantially uniform and can be relatively small in size—comparable to a critical dimension. Alternatively, the lateral dimensions C
1
, C
2
, and C
3
may vary from each other.
Turning to
FIG. 2
, openings
12
,
22
, and
32
, which may be of predetermined lateral dimension or of critical dimension, have been formed in dielectric layer
4
by exposure of the dielectric layer to plasma etch
8
. As shown in
FIG. 2
, lateral dimensions x
1
, x
2
, and x
3
of openings
12
,
22
, and
32
, respectively, may vary. It is to be noted that features in
FIGS. 1 and 2
are not drawn to scale, but are exaggerated in order to highlight, for example, potential differences between lateral dimensions x
1
, x
2
, and x
3
of openings
12
,
22
, and
32
.
It is thought that photoresist erosion may cause the lateral dimensions of openings formed in the underlying dielectric layers to vary from the design values of the critical dimensions. Photoresist erosion generally occurs more rapidly near the edges
1
of a wafer than at the center
3
. It is thought that this is due to higher temperatures at the wafer edges. The higher temperatures might result from a higher concentration of plasma
8
being present proximate the wafer edges than proximate the wafer center, as shown by the density of the arrows depicting plasma
8
in FIG.
2
. As the size of critical dimensions is reduced, the use of, for example, a CF
4
/CHF
3
/Ar/N
2
etchant gas mixture may result in openings with unacceptable dimensional uniformity. That is, the variation &Dgr;C
i
in the lateral dimension x
i
for the ith opening, where &Dgr;C
i
=x
i
—C
i
and C
i
is the critical dimension of the ith opening, may be considered unacceptable if |&Dgr;C
i
| exceeds a critical variation (e.g., a percentage of the value of C
i
specified by the operator).
It is therefore desirable that an alternative plasma etch chemistry and/or methodology be developed to impr

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