Planarized process for forming vias in silicon wafers

Details Planarized process for forming vias in silicon wafers Planarized process for forming vias in silicon wafers

1986-06-19

1987-11-24

Schor, Kenneth M.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156656, 156657, 1566591, C03C 1500, C23F 102, H01L 21312

Patent

active

047087706

ABSTRACT:
A process for forming vias in semiconductor structures includes the step of forming a pillar on an underlying dielectric layer prior to deposition of the metallization layer. The pillar is located above the diffusion region preferably and serves to provide substantially equal distances or heights for etching vias from the top planarized surface to the metallization layer deposited over the field oxide region and over the diffusion region.

REFERENCES:
patent: 3784424 (1974-01-01), Chang
patent: 4305760 (1981-12-01), Trudel
patent: 4381967 (1983-05-01), Sanders et al.
patent: 4451326 (1984-05-01), Gwozdz
patent: 4635347 (1987-01-01), Lien et al.

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