Planarized capacitor array structure for high density memory app

Details Planarized capacitor array structure for high density memory app Planarized capacitor array structure for high density memory app

1997-05-29

1998-06-23

Tsai, Jey

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438254, 438396, H01L 218242

Patent

active

057704996

ABSTRACT:
A planarized capacitor array (182) and method of forming the same for high density applications. A storage node contact (116) is formed through an interlevel dielectric (110) on a semiconductor body (102). Then, an oxide layer (170) having a first thickness is deposited over the interlevel dielectric (110) and the storage node contact (116). A nitride layer (172) having a second thickness is deposited over the oxide layer (170) to protect the oxide layer (170) during later processing. The nitride layer (172) and oxide layer (170) are then patterned and etched to form a storage plate cavity (180). The capacitor array (182) is then formed in the storage plate cavity (180). The capacitor array (182) has a height approximately equal to the sum of said first and second thicknesses, so that the surface of the top node of the capacitor array (182) is co-planar with the upper surface of the surrounding oxide
itride stack (170/172). Thus, the step height normally present between the capacitor array (182) and the peripheral area is avoided.

REFERENCES:
patent: 5389568 (1995-02-01), Yun
patent: 5597760 (1997-01-01), Hirota
patent: 5604146 (1997-02-01), Tseng

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