Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2005-09-15
2008-09-02
Lindsay, Jr., Walter L. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S425000, C438S427000, C438S589000, C438S700000, C257SE21507, C257SE21655, C257SE21704
Reexamination Certificate
active
07419878
ABSTRACT:
Power MOSFETs and fabrication processes for power MOSFETs use a continuous conductive gate structure within trenches to avoid problems arising from device topology caused when a gate bus extends above a substrate surface. The gate bus trench and/or gate structures in the device trenches can contain a metal/silicide to reduce resistance, where polysilicon layers surround the metal/silicide to prevent metal atoms from penetrating the gate oxide in the device trenches. CMP process can remove excess polysilicon and metal and planarize the conductive gate structure and/or overlying insulating layers. The processes are compatible with processes forming self-aligned or conventional contacts in the active device region.
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Chan Wai Tien
Cornell Michael E.
Williams Richard K.
Advanced Analogic Technologies (Hong Kong) Limited
Advanced Analogic Technologies, Inc.
Lindsay Jr. Walter L.
Millers David T.
Pompey Ron E
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