Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – By reaction with substrate
Reexamination Certificate
1998-04-14
2004-08-17
Nguyen, Thanh (Department: 2813)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
By reaction with substrate
C438S303000, C438S430000, C438S772000, C438S775000, C438S777000
Reexamination Certificate
active
06777346
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates, in general, to planarization methods and, more particularly, to a method and apparatus for filling gaps between metal lines in multilayer metallization structures.
2. Statement of the Problem
Integrated circuit technology has advanced through continuing improvements in photolithographic processing so that smaller and smaller features can be patterned onto the surface of the substrate. Spaces or gaps exist between these patterned features. Integrated circuit surfaces also contain trench or via structures protruding down into the surface. The lateral dimensions of such structures is hereinafter referred to as the width of the gap trench or via: the vertical dimension of such structures is referred to as the depth. The aspect ratio is the ratio of the depth to width. The smaller features, with smaller spaces between features, result in high aspect ratio gaps, trenches and vias. These high aspect ratio structures must be filled with an appropriate material before continued processing. This problem is acute in the case of multilayer metal (MLM) designs. In MLM designs each metal layer must be planarized by filling the gaps between metal features with dielectric before a subsequent metal layer can be formed and patterned.
When a deposited film is used to completely fill the high aspect ratio structure three different results can emerge. In one case, the deposited material fills the trench without leaving a seam or void. In a second case, a seam arises from the point where the sidewall layers merge during deposition. In a third case, a void arises if the deposition produces re-entrant profiles at earlier stages of the filling process. The first creates the highest reliability integrated circuits. The seams and voids are undesirable because chemicals or materials may be present in the seam or void to corrode or degrade the structure. Further, voids are rarely hermetically sealed, so subsequent exposure to chemicals or materials deposition can alter the material structure substantially.
Deposition onto patterned features is practiced at several stages and fabrication of semiconductor devices in integrated circuits. Most often the objective is to provide a highly conformal film or a void-free fill. Low pressure chemical vapor deposition (LPCVD) and plasma enhanced chemical vapor deposition (PECVD) are widely used to provide conformal deposition of thin films over three dimensional features. A number of CVD films are currently used in various steps in processing. Typically, sidewall coverage is not uniform along the height of a trench or a via. Low temperature plasma-enhanced deposition and etching techniques are used to form diverse materials including dielectric films such as silicon nitride and silicon dioxide and semiconductor films such as amorphous and polycrystalline silicon. The plasma used in the plasma-enhanced CVD process is a low pressure plasma that is developed in a radio frequency (RF) field. The RF plasma results in a very high electron temperature making possible the deposition of dense, good quality films at lower temperatures and faster deposition rates than are typically possible using purely thermally activated CVD processes.
Current CVD processes have important limitations. With high integration levels, higher aspect ratios are required, stretching the ability of known CVD processes. Seams and voids all endanger the manufacturability of semiconductor product due to the yield and reliability problems they present. Where higher growth temperatures improve conformality or profiles, other properties of the three dimensional structure may be degraded (i.e. abrupt doping profiles due to diffusion). Further, higher growth temperatures cannot be used after metallization.
Planarization processes are particularly difficult after metallization is applied to an integrated circuit. All processes subsequent to metal deposition must be performed at sufficiently low temperature such that the metal does not melt or vaporize. Conventionally this has limited post metallization processing to thin film deposition together with patterning or polishing those thin films. Oxidation processes are almost entirely unused after metal deposition.
Step coverage and filling of high aspect ratio gaps with CVD films is a continuing problem in the integrated circuit manufacturing industry. Decreasing costs for most IC products forces increasingly efficient production and higher throughput of film deposition processes. What is needed is a method and apparatus for highly conformal CVD deposition and planarization after deposit and patterning of metal films.
Other prior art planarization processes include deposit-etch-deposit processes whereby a thin film of an insulating material is deposited then etched or polished from the surface to mechanically planarize the film followed by subsequent deposit and etch processes until a planar surface is achieved. As metal line pitch is reduced, the deposit-etch-deposit processes leave voids between the metal lines that cannot be filled.
Another prior process is spin on glass (SOG) planarization. SOG uses a suspension of glass particles in an organic carrier that can be spun onto a wafer in a thin film using conventional photoresist tools. The organic carrier is then driven off in thermal processing and the glass reflowed to fill spaces between metal lines. Spin on glass planarization is plagued with via poisoning caused by contaminants in the spin on glass and the organic carrier that cannot adequately be removed during subsequent processing.
U.S. Pat. No. 5,182,221 issued to Sato on Jan. 26, 1993 describes an ECR-CVD process in which etching and deposition are simultaneously performed. In one embodiment, the Sato deposition process is performed in a single step with carefully controlled conditions to provide a ratio of vertical to horizontal deposition rate that will fill high aspect ratio trenches. The Sato process provides high quality via fill at the cost of increased control and reduced deposition rates. Further, because of high equipment costs associated with the ECR-CVD processes, they have limited applicability and are not heavily used in IC manufacturing.
A need exists for a process for filling spaces between pattern metallization features with dielectric using existing equipment technology that provides high quality void free via filling.
3. Solution to the Problem
The above identified problems and others are solved by a planarization method using a thin film of expandable material applied to a surface of patterned metal features. The expandable material is treated at low temperature to cause a volume increase and fill the spaces between metal features. In this manner the spaces between metal features are filled in a void-free, seam free-manner at temperatures well below the melting point of the metal features.
SUMMARY OF THE INVENTION
Briefly stated, the present invention involves a planarization process for filling spaces between patterned metal features formed over a surface of a semiconductor substrate. The patterned metal features are preferably coated with a dielectric barrier. The dielectric barrier is coated with an oxidizable material such as silicon to a thickness about half the depth of the space between metallized features. The oxidizable layer is then plasma oxidized using an RF or ECR plasma at low temperature with an oxygen or ozone ambient. Alternatively, a material that expands during nitridization is substituted for the oxidizable material and the step of plasma oxidation is replaced by a step of plasma nitridization. The plasma oxidation or nitridization is continued until the expandable material is converted to a dielectric and has expanded to fill the space between patterned metal features. Optionally, the process can be followed by a mechanical or chemical mechanical planarization step.
REFERENCES:
patent: 4323589 (1982-04-01), Ray et al.
patent: 4408387 (1983-10-01), Kiriseko
patent: 4527325 (1985-07-01), Geipel, Jr. et al.
patent: 4576829 (1986
Micro)n Technology, Inc.
Nguyen Thanh
Yoder Fletcher
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