Planarization of Josephson integrated circuit

Details Planarization of Josephson integrated circuit Planarization of Josephson integrated circuit

1991-04-04

1991-10-08

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156645, 156651, 156653, 156656, 156657, 1566591, 156667, 505728, 505820, H01L 21306, B44C 122, C23F 102, C03C 1500

Patent

active

050551582

ABSTRACT:
A method for fabricating Josephson integrated circuits and the circuit is described incorporating the steps of depositing layers of different materials to form a trilayer Josephson junction, etching to define a plurality of trilayer areas, depositing dielectric material thereover, and chemical-mechanical polishing to planarize the dielectric material down to provide a coplanar surface with the tops of the trilayer areas for subsequent interconnection. The invention overcomes the problem of poor quality Josephson junctions, low Vm's, and crevices or gaps in the upper coplanar surface between the trilayer area and the surrounding dielectric material.

REFERENCES:
patent: 4548834 (1985-10-01), Tsuge et al.
patent: 4904619 (1990-02-01), Yamada et al.
S. Nagasawa et al., "Planarization Technology for Josephson Integrated Circuits", IEEE Electron Devices Letter, vol. 9, No. 8, pp. 414-416, Aug. 1988.
M. Gurvitch et al., "High Quality Refractory Josephson Tunnel Junctions Utilizing Thin Aluminum Layers", Appl. Phys. Lett. 42(5), pp. 472-474, Mar. 1, 1983.
H. Kroger et al., "Selective Niobium Anodization Process for Fabricating Josephson Tunnel Junctions", Appl. Phys. Lett. 39(3), pp. 280-282, Aug., 1981.
M. Gurvitch et al., "Preparation and Properties of Nb Josephson Junctions with Thin Al Layers", IEEE Transaction on Magnetics, vol. Mag-19, No. 3, pp. 791-794, May 1983.
B. Davari, "A New Planarization Technique Using a Combination of RIE and Chemical Mechanical Polish (CMP)", IEEE, IEDM, pp. 61-64, 1989.

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