Planarization of a gate electrode for improved gate patterning o

Details Planarization of a gate electrode for improved gate patterning o Planarization of a gate electrode for improved gate patterning o

1993-08-12

1994-09-13

Powell, William

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156656, 1566591, 156662, 437192, 437193, 437233, H01L 21306, B44C 122, C23F 100, C03C 1500

Patent

active

053465873

ABSTRACT:
The present invention is a process for providing a planarized transistor gate on a non-planar starting substrate, by depositing a layer of planarized conductive polysilicon material overlying neighboring field oxide isolation regions such that the height of the conductive polysilicon material extends above the topology of the field oxide isolation regions; depositing a layer of conductive silicide material superjacent and coextensive the conductive polysilicon material; and then patterning the planarized conductive polysilicon material and the conductive silicide material thereby forming the planarized transistor gate.

REFERENCES:
patent: 4966868 (1990-10-01), Murali et al.
patent: 5030584 (1991-07-01), Nakata
patent: 5037772 (1991-08-01), McDonald
patent: 5264076 (1993-11-01), Cuthbert et al.

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