Planarization method on a damascene structure

Details Planarization method on a damascene structure Planarization method on a damascene structure

1998-08-28

2002-03-26

Whitehead, Jr., Carl (Department: 2822)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S633000, C438S672000, C438S692000

Reexamination Certificate

active

06362092

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 87109658, filed Jun. 17, 1998, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to formation of a damascene structure in semiconductor fabrication process, and more particularly to a planarization method included in fabricating a dual damascene structure to reduce dishing and oxide erosion phenomena.
2. Description of Related Art
A highly integrated semiconductor device usually includes at least two interconnect metal layers, called multilevel interconnects. Its purpose is to accord with a wiring line structure, which is a three-dimensional interconnection design to increase integration of devices. Fabrication of the multilevel interconnects usually includes a first interconnect metal layer on the lower level and a second interconnect metal layer on the upper level. These two interconnect metal layers carry their own interconnection structures and are electrically coupled together in a certain location. The first interconnect metal layer includes, for example, polysilicon or metallic material and is directly and electrically coupled to an interchangeable source/drain region of transistors on a semiconductor substrate. The other interconnections between device elements are accomplished by the second interconnect metal layer or more interconnect metal layers.
As the device dimension is reduced down to the deep-submicron level, problems may develop for the interconnection method described above. For example, if a plug to fill an opening is made of copper, then it induces a lot of problems when the copper plug is etched back, and it is difficult to choose a proper etchant. Moreover, the fabrication becomes more difficult. For example, a void or a trapping of impurities can occur due to a poor quality of step coverage when the metal layer is deposited into the plug or a dielectric layer is deposited over the metal layer. A conventional method called damascene is then proposed to solve above problems induced by a reduced device dimension at deep-submicron level and to automatically planarize the dielectric layer.
Currently, damascene technology, such as dual damascene technology, is widely used to fabricate interconnect metal layers. This dual damascene technology allows the fabrication of an integrated circuit device to be more stable and more advanced. A variety of metallic materials, such as aluminum, copper, or aluminum alloy, can be chosen. Therefore, the requirements of low resistance and low electro-migration for interconnect metal layer are easily satisfied by allowing various choices of metallic materials. The dual damascene technology is thereby widely used in very large scale integrated (VLSI) fabrication at a dimension less than 0.25 microns to fabricate an interconnect structure with high efficiency and high stability.
However, for the conventional dual damascene structure, when a large area is planarized by CMP process, a dishing phenomenon then occurs. Furthermore, an oxide erosion may occur on the high element density region to cause an electrical property shift.
FIGS. 1A-1D
are cross-sectional views schematically illustrating a conventional dual damascene process flow. The dual damascene structure is one example of damascene structure and is taken as an example for disclosure. In
FIG. 1A
, an inter-metal dielectric layer
12
including, for example, oxide is formed over a semiconductor substrate
10
. Then, a wide opening
14
is formed on the inter-metal dielectric layer
12
by photolithography and etching.
In
FIG. 1B
, a narrow opening
16
is formed in the inter-metal dielectric layer
12
within the wide opening
14
by photolithography and etching. The narrow opening
16
exposes the substrate
10
and has a narrower width than the width of the wide opening
14
.
In FIG.
1
B and
FIG. 1C
, a metal layer
18
is deposited over the substrate
10
so that the openings
14
,
16
are fully filled. The wide opening
14
has a larger width and thereby the photolithography resolution is not limited but causes a concave region
17
above the wide opening
14
.
In FIG.
1
C and
FIG. 1D
, a CMP process is performed to polish the metal layer
18
until the inter-metal dielectric layer
12
is exposed. The surface of the structure is also planarized. The top portion of the metal layer
18
is polished away and only the portion within the opening
14
is left. Since the concave region
17
exists originally, a little concave region
19
still exists after CMP process. The concave region
19
is called the dishing phenomenon.
The dishing phenomenon occurs when a CMP process is performed on the dual damascene structure. If the substrate includes a large number of the dual damascene structures, another phenomenon may further occur.
FIG. 2
is a cross-sectional view schematically illustrating several dual damascene structures formed on a semiconductor substrate after CMP process. In
FIG. 2
, several dual damascene structures
24
are formed on an inter-metal dielectric layer
22
, which is formed over a semiconductor substrate
20
. After CMP process, the inter-metal layer
22
has lower surface height at the central region and each of the dual damascene structures
24
has concave surface as usual but those dual damascene structures
24
at the central region also have lower surface height. This phenomenon is called the oxide erosion phenomenon.
Since planarization is still poor for the dual damascene structure after CMP process, it thereby affects the subsequent fabrication processes and further causes an electrical property shift. For example, if the surface height is not uniform, a pattern can not be precisely transferred onto a subsequent layer such as a next interconnect metal layer serving as an interconnect metal line or any kind of layers to be patterned.
SUMMARY OF THE INVENTION
It is therefore an objective of the present invention to provide a planarization method for a damascene structure in order to reduce the dishing and erosion phenomena so that the subsequent fabrication processes are not affected.
In accordance with the foregoing and other objectives of the present invention, a planarization method is included in fabrication of a damascene structure on a semiconductor substrate. The planarization method is performed after a dual damascene structure is semi-formed on a semiconductor substrate but before a CMP process is performed to polish a metal layer on the top of the substrate for planarization. The planarization method therefore starts by forming a dielectric layer over the metal layer. Next, a portion of the dielectric layer other than the dual damascene region is removed. Based on a polishing rate ratio of the dielectric layer to the metal layer, a CMP process is performed to planarize the substrate and exposes an inter-metal dielectric layer included in the dual damascene structure. The dual damascene structure is accomplished and the surface of the substrate is simultaneously planarized with a sufficiently good quality, in which the dishing and erosion phenomena are avoided.


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patent: 5187119 (1993-02-01), Cech et al.
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patent: 5665202 (1997-09-01), Subramanian
patent: 6037664 (2000-03-01), Zhao et al.
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