Planarization method for self-aligned contact process

Details Planarization method for self-aligned contact process Planarization method for self-aligned contact process

1996-06-03

2000-08-29

Jones, Dwayne C.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438631, 438697, 438699, 438700, 438702, 438760, 438740, 438959, H01L 2144

Patent

active

061108278

ABSTRACT:
A planarization method for self-aligned contact process which is suitable for use in DRAM processing. Prior to the formation of the bottom terminal layer of the capacitor, the substrate surface is first planarized, thus avoiding stringer effects and related bridging problems arising from an undulating surface profile, during subsequent etching of the defined pattern. Also according to the method of this invention, by covering the silicon substrate that has MOS transistors laid on top with first a deposition of an oxide layer, then an etch discriminatory layer, and finally a planarization layer, a substrate with a smooth, plane surface is obtained.

REFERENCES:
patent: 4954459 (1990-09-01), Avanzino et al.
patent: 5164340 (1992-11-01), Chen et al.
patent: 5188987 (1993-02-01), Ogino
patent: 5545581 (1996-08-01), Armacost et al.

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