Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-02-20
2002-05-21
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S275000, C438S279000, C438S697000, C438S760000
Reexamination Certificate
active
06391718
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 90100096, filed Jan. 3, 2001.
BACKGROUND OF THE INVENTION
1. Field of Invention
This invention relates to a planarization method. More particularly, the present invention relates to a planarization method for flash memory devices.
2. Description of Related Art
Flash memory device is an electrically-erasable-programmable-read-only memory device, which has the advantages of being programmable, erasable and the ability of retaining data after the power is off. A flash memory device is thus commonly used in personal computer and electronic devices. Flash memory device is also a non-volatile memory (NVM), which has the advantages of being small in dimension, speedy data retrieval and storage, and low power consumption. Furthermore, the erasing of data in a flash memory device uses the “block-by-block” method; therefore, it also has the advantage of having faster operational speed.
The basic structure of the memory cell region of a flash memory device includes a stacked gate structure, wherein the stacked gate structure comprises a tunnel oxide layer, a floating gate, a dielectric layer, a control gate and source/drain regions in the substrate on both sides of the stacked gate structure. In addition, at the peripheral of the memory cell region is the periphery circuit region, which includes peripheral devices that are used to write, to erase or to read data in the memory cell region.
The conventional fabrication method of a flash memory device includes depositing a dielectric layer on the substrate to cover the memory cell region and the peripheral circuit region after forming the memory cell region and the peripheral circuit region at the peripheral of the memory cell region. Chemical-mechanical polishing (CMP) is then conducted to form a planarized surface.
Using the conventional CMP process to planarize a flash memory device has several disadvantages. First of all, chemical-mechanical polishing a larger area is easier to control, for example, the area of the peripheral circuit region. However, chemical-mechanical polishing a smaller area, for example, the area of the memory cell region, is difficult to control. Hence, using chemical-mechanical polishing for planarization, it is difficult to control the polishing end point for the entire device. In addition, microscratches are easily induced on the device. Moreover, using chemical mechanical polishing to planarize an area with uneven surface levels, for example, the shallow trench isolation region, would easily have the polished debris remaining in the area.
SUMMARY OF THE INVENTION
The invention provides a method to planarize a flash memory device. The method does not require the application of chemical-mechanical polishing to accomplish the planarization of the flash memory device. The various disadvantages of chemical-mechanical polishing are thus prevented.
The present invention provides a planarization method for a flash memory device, wherein this method includes forming sequentially a polysilicon layer and a cap layer on a substrate. Thereafter, the cap layer and the polysilicon layer are patterned to form the peripheral circuit region and the memory cell region. A dielectric layer is then formed on the substrate, covering the cap layer. A portion of the dielectric layer is then removed to expose a part of the cap layer, such that the dielectric layer above the cap layer and the dielectric layer on both sides of the cap layer becomes separated. A portion of the dielectric layer in the peripheral circuit region is further removed, followed by forming a photoresist layer on the substrate, wherein a portion of the dielectric layer in the peripheral circuit region and in the memory cell region is exposed. The dielectric layer exposed by the photoresist layer is then removed, followed by removing the photoresist layer. The cap layer is subsequently removed to complete the planazation of the flash memory device.
According to the present invention, the planarization of a flash memory device is accomplished by etching. The common problems encountered in chemical-mechanical polishing, such as controlling the polishing end point, forming microscratches on the device surface and having polished debris remaining in areas with uneven surface levels, are prevented.
The present invention employs a photoresist layer, which only exposes a portion of the dielectric layer in the peripheral circuit region and in the memory cell region. Moreover, the dielectric layer in the peripheral circuit region and in the memory cell region is removed first, followed by removing the cap layer. As a result, the problems of having the dielectric layer detached and suspended in solvent during the removal of the cap layer, and having debris adhered to the wafer, which would lead to the formation of defects in the subsequent processes, are prevented.
According to the present invention, the dielectric layer in the peripheral circuit region and in the memory cell region is removed first, followed by removing the cap layer. The potential problem of contaminating the cleaning machine when the wafer is being cleaned, due to the suspension of the dielectric layer in the solvent when the cap layer is removed, is thus prevented.
The present invention employs a photoresist layer, which only exposes a portion of the dielectric layer in the peripheral circuit region and in the memory cell region. The dielectric layer in the peripheral circuit region and in the memory cell region is removed first, followed by removing the cap layer. The problem of having small pieces of the detached dielectric layer
106
a
suspending in solvent and adhering to the wafer and leading to defects in the subsequent processes is prevented.
According to the present invention, the dielectric layer in the peripheral circuit region and in the memory cell region is removed first, followed by removing the cap layer. The potential problem of contaminating the cleaning machine during the subsequent cleaning of the wafer due to the small pieces of the dielectric layer suspending in the solvent when the cap layer is removed is thus prevented.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 6004843 (1999-12-01), Huang
patent: 2001/0012226 (2001-08-01), Jeng et al.
Chaudhari Chandra
Chen Jack
Macronix International Co. Ltd.
Patents J. C.
LandOfFree
Planarization method for flash memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Planarization method for flash memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Planarization method for flash memory device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2874742