Planarization method and system using variable exposure

Details Planarization method and system using variable exposure Planarization method and system using variable exposure

1999-11-10

2002-08-27

Huff, Mark F. (Department: 1756)

Radiation imagery chemistry: process, composition, or product th

Imaging affecting physical property of radiation sensitive...

Forming nonplanar surface

C430S311000, C430S396000, C430S313000, C216S038000, C438S760000

Reexamination Certificate

active

06440644

ABSTRACT:

FIELD OF THE INVENTION
The following invention relates to planarizing a semiconductor surface for subsequent processing.
BACKGROUND OF THE INVENTION
A semiconductor integrated circuit includes multiple layers of various materials. One important consideration in creating a semiconductor integrated circuit is aligning all layers so that patterns match and accurate alignment is achieved. Alignment becomes even more critical as the features on a wafer are minimized. As features shrink in size, any misalignment or variation in processing which might have been acceptable for a larger element might lead to the failure of the smaller element. It is sometimes desirable that a layer be smooth in order, for example, to ensure uniform coverage of a subsequently formed layer. One way of smoothing a layer includes heating the applied layer near its melting point so that the layer begins to flow. This works well, for example, with a phosphorus-doped silicon dioxide layer when heated to temperatures above 800° C. However, when the highest allowable substrate temperature is less than the silicon dioxide flow temperature, heating and flowing as described would destroy the substrate.
An alternative technique exists which can be used to smooth the semiconductor surface.
FIGS. 1
,
2
A, and
2
B show the process known as planarization.
FIG. 1
shows a substrate with a poly-silicon feature
101
. coating feature
101
is phosphorus-doped silicon dioxide (commonly known as P-glass)
102
.
FIGS. 2A and 2B
show how a known planarization process functions. To planarize the abrupt steps found in layer
102
, a resist layer
103
coats the surface of the P-glass as shown in FIG.
2
A. The resist is etched away. During the etching process, the P-glass layer
102
is etched as well, converting the sharp steps into smoother shapes. This process, however, has the drawbacks of not adequately planarizing the surface. If one was to repeat the above process, the resulting surface level would be flatter, however more processing steps would be required.
SUMMARY OF THE INVENTION
The invention is based on the relationship between sub-resolution pattern density and resist thickness. A high pattern density minimizes the radiation that passes through a pattern mask. As pattern density increases, less actinic light is allowed through. In the case of positive resists, less light means fewer bonds are broken. After development, less resist is stripped away, yielding a greater resist thickness. The current system includes a multiple density portion pattern mask which is placed over a resist-coated substrate. The resist is exposed and processed. The resist is removed and an improved planarization state is achieved. The invention has been described with respect to using positive resists. It is equally adaptable for use with negative resists. Uses for the system and method disclosed include forming buried-strap layers and trench capacitors.


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