Planarization for interlayer dielectric

Details Planarization for interlayer dielectric Planarization for interlayer dielectric

1998-11-10

2000-11-07

Nelms, David

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438240, 438241, 438253, 438254, 438624, 437 52, 437 60, 437200, 437931, 437950, H01L 218244

Patent

active

061435961

ABSTRACT:
The method includes forming a first dielectric layer on a wafer having cell area and cell boundary. The first dielectric layer is etched to generate a plurality of holes. A polysilicon layer is next conformally deposited on the surface of the contact holes and on the first dielectric layer. A photoresist is coated on the polysilicon layer and into the holes. Next, a CMP (chemical mechanical polishing) is performed to remove the polysilicon layer that are over the first dielectric layer. The photoresist is then stripped, therefore forming a crown shape structure over the wafer. A second photoresist pattern is patterned on the first dielectric layer to cover the cell boundary, thereby leaving exposed the crown shape structure. Subsequently, an etching process is used to etch the first dielectric layer. Then, the second photoresist pattern is stripped. A further dielectric such as oxide layer is redeposited both on the cell area and the cell boundary to obtain a planar surface.

REFERENCES:
patent: 4879257 (1989-11-01), Patrick
patent: 5668036 (1997-09-01), Sune
patent: 5691223 (1997-11-01), Pittikoun et al.
patent: 5824581 (1998-10-01), Tseng

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