Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having junction gate
Reexamination Certificate
2009-03-16
2011-11-08
Coleman, William D (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having junction gate
C257SE21421
Reexamination Certificate
active
08053298
ABSTRACT:
This invention discloses an improved semiconductor power device includes a plurality of power transistor cells wherein each cell further includes a planar gate padded by a gate oxide layer disposed on top of a drift layer constituting an upper layer of a semiconductor substrate wherein the planar gate further constituting a split gate including a gap opened in a gate layer whereby the a total surface area of the gate is reduced. The transistor cell further includes a JFET (junction field effect transistor) diffusion region disposed in the drift layer below the gap of the gate layer wherein the JFET diffusion region having a higher dopant concentration than the drift region for reducing a channel resistance of the semiconductor power device. The transistor cell further includes a shallow surface doped regions disposed near a top surface of the drift layer under the gate adjacent to the JFET diffusion region wherein the shallow surface doped region having a dopant concentration lower than the JFET diffusion region and higher than the drift layer.
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Bhalla Anup
Hebert Francois
Ng Daniel S.
Alpha & Omega Semiconductor Ltd.
Coleman William D
Lin Bo-In
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