Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-09-03
1999-07-13
Nguyen, Tuan H.
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
H01L 21336
Patent
active
059239794
ABSTRACT:
A planar DMOS power transistor (MOSFET) fabricated using only three masking steps, resulting in a significant reduction in fabrication cost. The resulting device is in terms of operations similar to prior art devices formed using more masking steps. Both the source and body regions are formed by implantations through the identical openings in the polysilicon/gate oxide layers into the substrate. After a subsequent glass layer is deposited and masked to expose openings, body contact regions are implanted into the source regions by overdosing the source region dopant concentration. The third masking step is the metal mask which also forms a termination structure.
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Chang Mike F.
Pitzer Dorman C.
Wang Hong
Klivans Norman R.
Nguyen Tuan H.
Siliconix incorporated
Thompson Craig
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