Placement method for decoupling capacitors

Details Placement method for decoupling capacitors Placement method for decoupling capacitors

2006-04-25

2006-04-25

Tran, Thien F. (Department: 2811)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S239000, C438S386000, C438S399000

Reexamination Certificate

active

07033883

ABSTRACT:
A method for placing decoupling capacitors in an integrated circuit during placement and routing stage. In the placement method, a floor plan of the integrated circuit is created, and includes the relative locations of a plurality of functional units. A power mesh comprising a plurality power lines is then overlaid on the floor plan, and the floor plan is divided into a plurality of windows. A plurality of semiconductor cells are placed into a portion of the windows. It is then determined whether a residual area comprising two adjacent windows without functional units and semiconductor cells disposed therein and at least three parallel power lines running theretrough exists. A MOS capacitor is then placed in the detected residual area, serving as a decoupling capacitor.

REFERENCES:
patent: 6337593 (2002-01-01), Mizuno et al.
patent: 6748579 (2004-06-01), Dillon et al.

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