Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2007-08-07
2007-08-07
Elmore, Stephen C. (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S100000, C711S167000, C710S001000, C710S003000, C710S004000, C710S026000, C365S230010, C365S230030, C365S230040, C365S230090
Reexamination Certificate
active
10850719
ABSTRACT:
The invention describes and provides pipelining of addresses to memory products. Addresses are pipelined to multibank memories on both rising and falling edges of a clock. Global Address Supervisor pipelines these addresses optimally without causing bank or block or subarray operational conflicts. Enhanced data through put and bandwidth, as well as substantially improved bus utilization (simultaneously), can be realized. In peer-to-peer connected systems, significant random data access throughput can be obtained.
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Elmore Stephen C.
Kim Daniel
S. Aqua Semiconductor LLC
Schwabe Williamson & Wyatt P.C.
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