Pipelined microprocessor with efficient self-modifying code dete

Details Pipelined microprocessor with efficient self-modifying code dete Pipelined microprocessor with efficient self-modifying code dete

1997-10-16

1999-12-28

De Cady, Albert

Electrical computers and digital processing systems: processing

Processing control

Branching

712205, G06F 938

Patent

active

060095164

ABSTRACT:
A microprocessor (10) and system (2) are disclosed, in which capability for the detection and handling of modifications of instructions potentially in the pipeline is implemented. The microprocessor (10) includes a self-modifying code (SMC) unit (50) that includes a fetch address window maintenance unit (52), a write comparator (54) associated with each load/store unit (40) in the microprocessor (10) that performs writebacks to memory (16, 11, 5), and a shared write comparator (55). The fetch address window maintenance unit (52) includes a minimum latch (60) that stores the lowest fetch address since a pipeline flush or machine reset, and a maximum latch (62) that stores the highest fetch address since flush or reset, and updates the minimum and maximum latches (60, 62) upon detecting that the current fetch address (LASTFA) falls outside of the current window. The write comparators (54) compare each new writeback address (LSxADR) to the minimum and maximum fetch addresses (MINFA, MAXFA) from the minimum and maximum latches (60, 62), respectively. In response to the writeback address (LSxADR) falling within the window, an exception sequence is initiated to flush the pipeline. Write comparators (54, 55) also compare the current fetch address (LASTFA) against the current writeback address and against the addresses of pending, but not completed, writebacks, to determine if a conflict exists between the fetched instruction and the pending writebacks.

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