Pipe latch circuit for outputting data with high speed

Details Pipe latch circuit for outputting data with high speed Pipe latch circuit for outputting data with high speed

2003-07-16

2004-11-02

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

With shift register

C365S189020, C365S233100

Reexamination Certificate

active

06813195

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to semiconductor memory devices. More particularly, the invention relates to a pipe latch circuit that receives input data from the cell area, latches the data, and outputs the data as output to external circuitry.
DESCRIPTION OF THE PRIOR ART
In general, a synchronous memory device requires a pipe latch circuit for continuous data output. A pipe latch circuit stores the data received from the cell area and sequentially outputs them according to the synchronization signals from a clock. A pipe latch circuit controller is used to control this pipe latch circuit. A pipe latch circuit controller is a device that provides control for sequentially storing the data received from the cell area according to the synchronization signals from a clock and outputting them.
FIG. 1
is a block diagram of a typical DDR (Double Data Rate) Synchronous memory device.
In
FIG. 1
, the DDR Synchronous memory device comprises a row address input
400
for receiving, decoding and outputting row addresses, a column address input
300
for receiving, decoding, and outputting column addresses, a cell area
500
for outputting data according to the signals from the row address input
400
and column address input
300
, an instruction interpreter
600
for receiving and decoding clock signals and instruction signals, a pipe latch circuit
100
for sequentially receiving data output from the cell area
500
and outputting to the output buffer, a pipe latch circuit controller
200
for controlling the pipe latch circuit
100
according to the signals received from the instruction interpreter
600
and the clock, and an output buffer
700
for receiving and outputting the outputs from the pipe latch circuit
100
as output data to external circuits.
In DDR memory devices where data is outputted on rising edges as well as falling edges, the pipe latch circuit receives even-numbered data and odd-numbered data from the cell area
500
separately, and sends them to the output buffer
700
as rising edge data and falling edge data, respectively. The even-numbered data and odd-numbered data are received from the cell area
500
by the pipe latch circuit
100
, and outputted in synchronization with the rising edges and falling edges of external clock signals.
Meanwhile, the pipe latch circuit
100
comprises a plurality of registers whose number depend on the number of data to be received and latched, and the CAS latency of the memory device. Also, there are serial pipe latch circuits which use registers in series, and parallel pipe circuits which use registers in parallel.
FIG. 2A
is a block diagram of a parallel pipe latch circuit comprising registers in parallel, according to the prior art.
With reference to the
FIG. 2A
, the pipe latch circuit
100
a
comprises a plurality of registers connected in parallel
100
a
for receiving even-numbered data, a plurality of registers connected in parallel
20
′_
1
,
20
′_
2
, . . . ,
20
′_n for receiving odd-numbered data, a plurality of path circuits
10
_
1
,
10
_
2
, . . . ,
10
_n provided at the stage preceding the registers
20
_
1
,
20
_
2
, . . . ,
20
_n,
20
′_
1
,
20
′_
2
, . . . ,
20
′_n for storing the received even-numbered data into the registers
20
_
1
,
20
_
2
, . . . ,
20
_n in response to n even-numbered input control signals (
1
~n), a plurality of path circuits
10
′_
1
,
10
′_
2
, . . . ,
10
′_n provided at the stage preceding the registers
20
_
1
,
20
_
2
, . . . ,
20
_n,
20
′_
1
,
20
′_
2
, . . . ,
20
′_n for storing the received even-numbered data into the registers
20
′_
1
,
20
′_
2
, . . . ,
20
′_n in response to n odd-numbered input control signals
1
~n, n multiplexers
30
_
1
~
30
_n for selectively outputting even-numbered data and odd-numbered data from each register
20
_
1
,
20
_
2
, . . . ,
20
_n,
20
′_
1
,
20
′_
2
, . . . ,
20
′_n, 2n path circuits
40
_
1
,
40
_
2
,
40
_n,
40
′_
1
,
40
′_
2
, . . . ,
40
′_n provided at the output stages of the multiplexers
30
_
1
~
30
_n for outputting data from the multiplexers
30
_
1
~
30
_n as rising edge data or falling edge data.
FIG. 2B
is a block diagram of a pipe latch circuit controller
200
a
for the pipe latch circuit
100
a
shown on FIG.
2
A.
In
FIG. 2B
, the pipe latch circuit controller
200
a
receives clock signals and data output timing control signals, and outputs 2n output control signals and n multiplexer selection signals. The 2n control signals include n control signals for even-numbered data, and n control signals for odd-numbered data.
In the following, the operation of a parallel pipe latch circuit is explained with reference to FIG.
2
A and FIG.
2
B.
First, when the data from the corresponding read addresses are sent from the cell area to the pipe latch circuit
100
a
, the 2n path circuits
10
_
1
,
10
_
2
, . . . ,
10
_n,
10
′_
1
,
10
′_
2
, . . . ,
10
′_n are sequentially turned on, in response to the n even-numbered input control signals
1
~n and n odd-numbered input control signals
1
~n. As the path circuits are turned on, the even-numbered data and odd-numbered signals are sequentially stored in the registers
20
_
1
,
20
_
2
, . . . ,
20
_n,
20
′_
1
,
20
′_
2
, . . . ,
20
′_n.
Subsequently, the n multiplexers
30
_
1
,
30
_
2
, . . . ,
30
_n output data from the registers
20
_
1
,
20
_
2
, . . . ,
20
_n,
20
′_
1
,
20
′_
2
, . . . ,
20
′_n as rising edge data or falling edge data selectively.
Subsequently, the n odd-numbered output control signals (
1
~n) and n even-numbered output control signals (
1
~n) from the pipe latch circuit controller (
200
a
) selectively turn on the path circuits
40
_
1
,
40
_
2
, . . . ,
40
_n,
40
′_
1
,
40
′_
2
, . . . ,
40
′_n, causing the output data from the n multiplexers
1
~n passed to the output buffer (ref.
700
FIG.
1
).
The above described parallel pipe latch circuit
100
a
has the advantage of outputting data in high speed, because input data is latched only once and outputted in response to the output control signals. However, the parallel pipe latch circuit
200
a
has a disadvantage in that the pipe latch circuit controller
200
a
becomes complex because it has to generate and output input control signals and output control signals separately.
For example, if we implement the pipe latch circuit using 16 registers, the controller is required to generate 16 input control signals (8 for even-numbered input control signals and 8 for odd-numbered input control signals) and 16 output control signals (8 for even-numbered output control signals and 8 for odd-numbered output control signals) each with different timing. Also, in this case, the parallel pipe latch circuit requires 8 multiplexers. The multiplexers require large footprint, so a parallel pipe latch circuit having a plurality of multiplexers requires large sized integrated circuit chip.
In order to solve the problem, a serial pipe latch circuit consisting of a plurality of registers connected in series is sometimes used because of its smaller footprint and simpler control structure.
FIG. 3
is a block diagram of a serial pipe latch circuit
100
b
consisting of registers connected in series and a pipe latch circuit controller
200
b.
In
FIG. 3
, the serial pipe latch circuit
100
b
comprises
a plurality of registers
50
_
1
,
50
_
2
, . . . ,
50
_n connected in series for receiving even-numbered data and delivering them sequentially, a plurality of path circuits
60
_
1
, . . . ,
60
_n−1 provided between the registers
50
_
1
,
50
_
2
, . . . ,
50
_n for delivering the data to the registers at the next stage, a plurality of registers
50
′_
1
,
50
′_
2
, . . . ,
50
′_n connected in series for receiving odd-numbered data and delivering them sequentially, a plurality of path circuits
60
′_
1
, . . . ,
60
′_n&min

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