Pillar CMOS structure

Details Pillar CMOS structure Pillar CMOS structure

1998-01-20

2000-08-08

Bowers, Charles

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438209, 438212, 438213, 438227, H01L 218238

Patent

active

061001236

ABSTRACT:
A method of forming a pillar CMOS FET device, especially an inverter, and the device so formed is provided. The method includes forming abutting N wells and P wells in a silicon substrate and then forming N.sup.+ and P.sup.+ diffusions in the P and N wells respectively. A unitary pillar of the epitaxial silicon is grown on the substrate having a base at the substrate overlying both the N and P wells and preferably extending at least from said N.sup.+ diffusion to said P.sup.+ diffusion in said substrate. The pillar terminates at a distal end. An N well is formed on the side of the pillar overlying the N well in the substrate and a P well is formed on the side of the distal end of the pillar overlying the P well on the substrate and abuts the N well in the pillar. A P.sup.+ diffusion is formed in the N well in the pillar adjacent the distal end and a N.sup.+ diffusion is formed in the P well in the pillar adjacent the distal end. A gate insulator dioxide is formed over both sides of the pillar and gate electrodes are formed over the gate insulators.

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IBM Technical Disclosure Bulletin, "Structures and Layout of a New Self-Aligned Pillar CMOS Logic Gate and SRAM Cell," vol. 32, No. 9A, Feb. 1990. pp. 338-340.
IBM Technical Disclosure Bulletin, "New Self-Aligned Pillar CMOS Technology--Structures and Fabrication Methods," vol. 32, No. 8A, Jan. 1990. pp. 144-145.

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